Ide (Pata) Connector - HP Compaq dc7600 MT Technical Reference Manual

IDE Bus Master Control Registers
The IDE interface can perform PCI bus master operations using the registers listed in Table 5-2.
These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI
configuration register 20h in the previous table.
I/O
Address
Offset (Bytes)
00h
02h
04h
08h
0Ah
0Ch
NOTE:
Unspecified gaps are reserved, will return indeterminate data, and should not be written to.

IDE (PATA) Connector

The SFF, ST, MT, and CMT form factors provide a standard 40-pin connector for a primary IDE
device and in most factory configurations connects to a optical drive (CD or DVD). Some signals
are re-defined for UATA/33 and higher modes. Device power is supplied through a separate
connector.
Figure 5-1. 40-Pin IDE (PATA) Connector.
✎
The USDT form factor does not include 40-pin IDE connctor. The IDE interface and hard drive
power signals are both a part of the MultiBay interface used on the USDT form factor.
Technical Reference Guide
Table 5-2.
IDE Bus Master Control Registers
Size
Register
1 Bus Master IDE Command (Primary)
1 Bus Master IDE Status (Primary)
4 Bus Master IDE Descriptor Pointer (Pri.)
1 Bus Master IDE Command (Secondary)
2 Bus Master IDE Status (Secondary)
4 Bus Master IDE Descriptor Pointer (Sec.)
0000 0000h
0000 0000h
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Input/Output Interfaces
Default
Value
00h
00h
00h
00h
5-3