Integrated Peripherals Option - ECS L7VTA3 Manual

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Table Of Contents

Table of Contents

L7VTA3 V3.1a

PCI 1/2 Master 0 WS Write (Enabled)

When enabled, writes to the PCI bus are executed with zero wait states, pro-

viding faster data transfer.

PCI 1/2 Post Write (Enabled)

When enabled, writes from the CPU to PCU bus are buffered, to compensate

for the speed differences between the CPU and PCI bus. When disabled, the

writes are not buffered and the CPU must wait until the write is complete be-

fore starting another write cycle.

PCI Delay Transaction (Disabled)

The mainboard's chipset has an embedded 32-bit post write buffer to support

delay transactions cycles. S elect Enabled to support compliance with PCI

specification version 2.1.

Press <Esc> to return to the previous screen.

Memory Hole (Disabled)

This item is used to reserve memory space for ISA expansion cards that re-

quire it.

System BIOS/Video RAM Cacheable (Disabled)

These items allow the video and system to be cached in memory for faster

execution. Leave these items at the default value for better performance.