Panasonic PV-DV102PN Service Manual page 127

VIDEO SIGNAL PROCESS II BLOCK DIAGRAM
MAIN C.B.A.
IC3201 (FORMATTING/EQUALIZER)
TO/FROM VIDEO I
80
DBR (0-3)
SIGNAL PROCESS
BLOCK DIAGRAM
83
(FROM IC6001(71))
RESET(L)
(FROM IC6001(63))
XWEH
FROM SYSTEM
(FROM IC6001(64))
CONTROL
XWEL
BLOCK DIAGRAM
(FROM IC6001(62))
XRE
(FROM IC6001(61))
ADDRESS STROBE
27MHz CLOCK
24.576MHz CLOCK
TO/FROM VIDEO I ADM (0-15)
SIGNAL PROCESS
3 BLOCK DIAGRAM
DBP (0-3)
MODULATOR
/DEMODULATOR
AGC CONTROL
VITERBI EQUALIZER A/D CONVERTER
ATF DET BPF A/D CONVERTER
MICROCONTROLLER
INTERFACE
D/A CONVERTER
ADDRESS 27MHz
STROBE CLOCK
RESET(L) RESET(L) XWEH XWEL XRE
52 54 55 57 58 61 64
30 4 78 77 74 75
66 68 70 73
IC5001 (HEAD AMP)
41 8
LOGIC
REC CLOCK 45 10
AGC
27 3
DET
AGC
AMP 8 6 1
AMP
AMP 5 39
REC-C CONTROL 29 35
EQ HOLD 43 11
REC CONTROL 44 15
HEAD SW PULSE 2 38 16
HEAD SW PULSE 1 36 17 LOGIC
PB(H) 42 18
REC ON/OFF CONTROL 39 19
(FROM SAFETY TAB SW)
14
S-TAB ON(L)
20
88
TO SYSTEM
(TO IC6001(86))
CONTROL
HEAD SW IC3202 (IEEE1394 INTERFACE)
BLOCK DIAGRAM PULSE 1
73 XWEL
71 XRE
74 ADDRESS STROBE
94 27MHz CLOCK
28 24.576MHz CLOCK
50
51
53
56
58
MICROCONTROLLER
INTERFACE
61
63
66
68
69
75 DATA (4 BIT)
76
79
81
REC VIDEO SIGNAL PB VIDEO SIGNAL REC AUDIO SIGNAL
DRIVE GCA 27
CH1
26
HEAD
28
AMP
29
31
CH2
30
HEAD
43 AMP AMP 32
AMP
33
LPF
41
V1 0.2Vp-p V1 4Vp-p
0.1V 5µs 2V 2ms
14
15
IEEE1394
INTERFACE
17
18
VIDEO SIGNAL PROCESS II BLOCK DIAGRAM
PB AUDIO SIGNAL
CYLINDER UNIT
FP5
4
CH 1
FP5
HEAD
5
FP5
3 CH 2
HEAD
FP5
2
B2
ENVELOPE
13
B2 TO INTERFACE BOARD
HEAD SW
PULSE (FOR EVR ADJUSTMENT)
14
B2
ATF
11
REAR C.B.A.
JK7003
DV JACK
B1 B1201
1 TPB(-)
14 14
B1 B1201
2 TPB(+)
15 15
B1 B1201
3 TPA(-)
27 27
B1 B1201
4 TPA(+)
26 26
5 GND
PV-DV102/PV-DV202/PV-DV402