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Chapter 3
Bank Interleave
If you set this item to Enabled, BIOS will set the bank interleave in 2 way or 4
way based on the configuration of SPD EEPROM.
DRAM Timing by SPD
If the setting is set to "Yes", the BIOS will set "SDRAM CAS Latency" and
"DRAM Clock" to follow the SPD configuration of memory modules
automatically. If the setting is set to "No", you can change the settings of
"SDRAM CAS Latency" and "DRAM Clock" as you want.
SDRAM CAS Latency
The option controls the CAS latency, which determines the timing delay
before SDRAM starts a read command after receiving it. Settings: Auto, 2, 3
(clock cycles). 2 increases system performance while 3 provides more stable
system performance. Auto allows BIOS to determine the best CAS latency
length.
DRAM Clock
The chipset supports synchronous and asynchronous mode between host
clock and DIMM clock.
Host CLK
Host CLK+33M
If you install the CPU with 133MHz FSB, the item will not appear in the BIOS.
Memory Hole
In order to improve performance, certain space in memory can be reserved
for ISA cards. This memory must be mapped into the memory space below
16 MB.
Enabled
Disabled
P2C/C2P Concurrency
This item allows you to enable or disable the PCI to CPU, CPU to PCI
concurrency.
DIMM clock equal to host clock
DIMM clock equal to 133MHz
Memory hole supported.
Memory hole not supported.
3-12
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