JVC KD-R491 Schematic Diagrams page 29

Pin No. Pin Name
109 Vcc
110 MDATA
111 TU_RST
111 NC
112 PVcc
113 SXM_PWR
113 NC
114 Vss
115 DRV_CNT
116 BEEP
117 DRV_Lo/Ej
118 PCB_TEST_MODE
118 WDT
119 SW2
119 DEBUG_2B
119 Field Test 2
120 BLKCK
120 Field Test 1
I/O Application
- Power supply
O Microcontroller Command Data Signal
O HELIO/CAYMAN (HD) Reset
O No Use (For non DAB/HD model)
- Power supply for I/O circuits
O Power Supply for SXM (For SXM model only)
O No Use (for non SXM model)
- GND
O Loading Motor Control Output
O Output for Beep Tone Generator
O Loading Motor Control Output
I PCB Test Mode Switch
O Watch Dog Timer output
I CD Mecha SW2
O For Debug
O RDS data log output (standby for field test)
I Sub-Code Block Clock Signal
O RDS data log output (standby for field test)
(No.MA665<Rev.001>)10/33
Processing/Operation/Descrip-
tion
L: Reset ON / H: Reset OFF
L: PWR Off / H: PWR On
H (Pulse): BEEP / L: OFF
L: Normal Mode / H: Check Mode
(After Reset software need to
check the pin input. If detect high it
should enter Serial Number mode)
L: Normal Mode / H: Reset by WDT