JVC KD-R491 Schematic Diagrams page 27

Pin No. Pin Name
32 ENC1
33 REMO
34 STAT
35 SW1
35 DEBUG_2A
36 PVcc
37 NC
38 Vss
39 RESET
40 Vss
41 PLLVcc
42 PAN_DET
42 NC
43 Vcc
44 EXTAL
45 XTAL
46 Vss
47 Vss
48 PVcc
49 D-0
50 D+0
51 ASEMD
52 PSW
53 NC
54 STAGE2
54 STEERING_REMO2
55 STAGE1
55 STEERING_REMO1
56 TEL_MUTE
56 LINE_MUTE
56 NC
57 DC_ERR1
58 Avss
59 Avcc
60 Avref
61 TRST
62 ASEBRKAK/ASEBRK
63 TDO
64 TDI
65 TMS
66 TCK
67 NC
68 NC
69 PVcc
70 SPBCLK
71 Vss
I/O Application
I Volume Encoder Pulse Input 1
I Remocon Input
I DSP Status Signal
I CD Mecha SW1
O For Debug
- Power supply for I/O circuits
O No Use
- GND
I Reset Input
- GND
- Power supply for PLL
I Panel Detection input
I No Use (for non detachable model)
- Power supply
I High Speed Clock 12MHz
O High Speed Clock 12MHz
- GND
- GND
- Power supply for I/O circuits
I/O USB Data- 0
I/O USB Data+ 0
I ASE Mode Select Pin
I CD Mecha Position Setting SW (Reset Switch)
I No Use (for non BT model)
I Model Selecting Input 2
I OE Remote In 2 (for DOP models)
I Model Selecting Input 1
I OE Remote In 1 (for DOP models)
I Tel Mute Detection Input (for JVC Model)
I Line Mute Detection Input (For KWD Model)
I No Use (for non support Tel mute model)
I Detect DC Offset Error from EVOL IC
- GND
- Power Supply
- Reference Power Supply
I Debugging Interface. Reset Input.
I/O Emulator Break Mode Acknoledge/Break Input
O Debugging Interface. Serial Output for Instructions and
Data
I Debugging Interface. Serial Input for Instructions and
Data
I Debugging Interface. Test Mode Select Signal Input.
I Debugging Interface. Test Clock Input.
O No Use
I No Use
- Power supply for I/O circuits
O FLASH SPI Multi I/O Bus Clock output
- GND
(No.MA665<Rev.001>)8/33
Processing/Operation/Descrip-
tion
L (Pulse): Remote control data / H:
Standby
L: Panel Attached / H: Panel De-
tached
Refer to respective spec
Refer to respective spec
Refer to respective spec
Refer to respective spec
L: DC Error ON / H: DC Error OFF