Intel 6 Series User Manual page 10

Term
Infrared Data
Assoc.
Intel ® MVP 7.0
Inter-Symbol
Interference
Mott Canyon IV
Network
Overshoot
Pad
Pin
Power-Good
Ringback
RJ45
System Bus
Setup Window
Simultaneous
Switching Output
2 nd Generation Intel ® Core™ Processor with Intel
User Guide
10
The Infrared Data Association (IrDA) has outlined a specification for serial
communication between two devices via a bidirectional infrared data port.
The CRB has such a port and it is located on the rear of the platform
between the two USB connectors.
®
The Intel Mobile Voltage Positioning specification for the 2
Intel ® Core™ Processor Family. It is a DC-DC converter module that
supplies the required voltage and current to a single processor.
Inter-symbol interference is the effect of a previous signal (or transition)
on the interconnect delay. For example, when a signal is transmitted
down a line and the reflections due to the transition have not completely
dissipated, the following data transition launched onto the bus is affected.
ISI is dependent upon frequency, time delay of the line, and the reflection
coefficient at the driver and receiver. ISI may impact both timing and
signal integrity.
This Add-in card enables Intel
The network is the trace of a Printed Circuit Board (PCB) that completes
an electrical connection between two or more components.
The maximum voltage observed for a signal at the device pad, measured
with respect to VCC.
The electrical contact point of a semiconductor die to the package
substrate. A pad is only observable in simulations.
The contact point of a component package to the traces on a substrate,
such as the motherboard. Signal quality and timings may be measured at
the pin.
"Power-Good," "PWRGOOD," or "CPUPWRGOOD" (an active high signal)
indicates that all of the system power supplies and clocks are stable.
PWRGOOD should go active at a predetermined time after system
voltages are stable and should go inactive as soon as any of these
voltages fail their specifications.
The voltage to which a signal changes after reaching its maximum
absolute value. Ringback may be caused by reflections, driver oscillations,
or other transmission line phenomena.
A type of registered jack.
The System Bus is the microprocessor bus of the processor.
The time between the beginning of Setup to Clock (TSU_MIN) and the
arrival of a valid clock edge. This window may be different for each type of
bus agent in the system.
Simultaneous Switching Output (SSO) effects are differences in electrical
timing parameters and degradation in signal quality caused by multiple
signal outputs simultaneously switching voltage levels in the opposite
direction from a single signal or in the same direction. These are called
odd mode and even mode switching, respectively. This simultaneous
switching of multiple outputs creates higher current swings that may
cause additional propagation delay ("push-out") or a decrease in
propagation delay ("pull-in"). These SSO effects may impact the setup
and/or hold times and are not always taken into account by simulations.
System timing budgets should include margin for SSO effects.
® 6 Series Chipset Development Kit
About This Document
Definition
®
High Definition Audio functionality.
Document Number: 325208-001
nd
generation
March 2011