Intel 6 Series User Manual page 23

Development Kit Features
Feature
Video Cables
Video
Video
Video
Video
Video
Video
PCI
PCIe
On-Board LAN
BIOS (SPI)
March 2011
Document Number: 325208-001
Development Board
Implementation
1x 24-bit dual-channel LVDS
interface
Embedded display port
Display Port
HDMI
DMC
SDVO
CRT
No slots on-board
8x PCIe x1 lanes from the Intel 6
Series chipset
Intel 82579 Gigabit Ethernet PHY
(Lewisville) supported
SPI flash devices
nd ®
2 Generation Intel Core™ Processor with Intel
Description
50-pin connector (J7D3) on-board;
cables from Intel 5 series-M chipset-
based platform development boards
can be re-used.
x4 eDP from Intel ® Core™ i7/i5
processor connected to on-board
embedded display port (eDP)
connector at J4E1.
Port B: Connected to x16 connector
at J8C2. Requires Eaglemont add-in
card Port C: Switchable connection
to x16 connector at J8C2 or docking
connector at J9C1 Port D: Default
connection to Display Port connector
at J5A1.
Port B: Connected to x16 connector
at J8C2. Requires Eaglemont add-in
card Port C: Switchable connection
to x16 connector at J8C2 or docking
connector at J9C1 Port D:
Unpopulated stuffing option
connection to HDMI connector at
J3A1.
Display Mini PCIe connector is
provided on-board (J7M1). Display-
Port D is optionally connected to
DMC. PCIe – Port-8 is by default
connected to DMC.
Port B: Connected to x16 connector
at J8C2. Requires ADD2N add-in
card.
On-board right-angled CRT
connector
Not supported by the Intel 6 Series
chipset.
PCIe Gen 2.0 Compliance, 5 GT/s
speed; four ports to x1 PCIe slots;
one port to x4 slot, one lane to
®
Intel 82579 Gigabit Ethernet
Controller LAN, one lane to docking
by default, one lane to display Mini
PCIe.
EU7M1 is the PHY on-board and
J4A1is the LAN connector.
Support for multi-vendor SPI 2x 8-
MB SOIC-8 parts provided on-board.
Supports multi-package (SOIC-8
®
6 Series Chipset Development Kit
User Guide
23