Bose BUILT-INvisible TA-1 Service Manual page 13

Digital Signal Processor (DSP) PCB (continued)
Codec (continued)
The codec generates three output signals, either from the 11.2896 MHz crystal, or from the input
S/PDIF bitstream;
• a serial bit stream containing the 20-bit audio data.
• a bit_clock, which indicates when to sample the serial bit stream.
• and a frame_clock, which indicates the start of an audio sample.
In addition, there is a serial data input (6 20-bit audio samples) to the codec, with timing that
corresponds exactly to the timing of the serial data output. These four signals (data out, data in,
bit_clock, and frame_clock) are used by the serial ports on the DSPs. The timing of the data flow
into and out of the DSP subsystem is driven entirely by the codec; the serial ports on the DSP
run asynchronously to the 40 MHz clock which drives the DSPs.
DSPs
The DSPs [DSP1, sheet 3 C/D7; DSP2, A/B7] are Analog Devices 21061L general purpose
floating point digital signal processors, each capable of about 40 MIPs of performance.
Two are required to provide enough MIPs for:
• AC-3 decoding.
®
• Videostage .
• bass management.
• six channels of speaker equalization.
• tone controls.
The DSPs have no internal ROM; at boot time they load themselves from the external PROM
U401 [sheet 3, C2]. This boot process is more or less automatic; i.e., no intervention from the
microcontroller is required (although the microcontroller has control of the DSP reset line).
The 21061L processors are designed to be bussed together, which accounts for the relatively
large number of pins found on each DSP (240).
For instance, the signals required to connect the DSPs to each other and to the boot PROM
include:
• an external data address buss (32 bits, of which 24 are used).
• an external data buss (48 bits, of which 16 are used).
• buss control signals (buss priority, address and r/w strobes, etc).
Also, there are 30 power and 30 ground pins on each DSP, and a 40 MHz clock oscillator (U400,
crystal CR400, and associated components) which drives both processors.
THEORY OF OPERATION
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