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ECC Mode
Select Enabled or Disabled ECC (Error Correcting Code), according to
the type of the installed DRAM.
AGP Aperture Size
This option determines the effective size of the graphics aperture
used in the particular PAC configuration. The AGP aperture is memory-
mapped, while graphics data structure can reside in a graphics aperture. The
aperture range should be programmed as not cacheable in the processor
cache, accesses with the aperture range are forwarded to the main memory,
then PAC will translate the original issued address via a translation table
that is maintained on the main memory. The option allows the selection of
an aperture size of 4MB, 8MB, 16MB, 32MB, 64MB, 128MB, and 256MB.
Delay Transaction
During Enabled, the chipset delay transaction mechanism will enable
the chipset to target the PCI transaction. A read cycle from Host to PCI is
immediately retrieved due to any pending PCI to DRAM cycle. During
Disabled, a read cycle from Host to PCI is waited until time-out due to any
pending PCI to DRAM cycle.
CPU to PCI Write Buffer
This item allows you to Enable or Disable the CPU to PCI Write
Buffer. The default setting is Enabled.
PCI Dynamic Bursting
This setting allows you to Enable or Disable PCI Dynamic Bursting
Function. The default setting is Enabled.
PCI Master 0 WS Write
Enabled
Disabled
The default setting is Enabled.
Zero wait-state response
One wait-state response
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