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Bank 0/1 DRAM Timing
Bank 2/3 DRAM Timing
Bank 4/5 DRAM Timing
The DRAM timing is controlled by the DRAM Timing Registers. The
Timings programmed into this register are dependent on the system design.
Slower rates may be required in certain system designs to support loose
layouts or slower memory.
SDRAM Cycle Length
This item allows you to select the SDRAM cycle length. The set-
tings are 2 or 3.
DRAM Read Pipeline
This item sets the timing for pipeline burst mode read from DRAM.
The default setting is Enabled.
Cache Rd+CPU wt Pipeline
This item can enabled the pipelining of Cache read and CPU write
cycle. The default setting is Enabled.
Cache Timing
This field allows you to determine the Cache burst mode timing.
Fast
Fastest
Video BIOS Cacheable
Select Enabled allows caching of the system BIOS ROM at C0000h-
F7FFFh, resulting in better video performance. However, if any program
writes to this memory area, a system error may result.
Enabled
Disabled
Cache burst mode timing are 31112111.
Cache burst mode timing are 31111111.
Video BIOS access cached
Video BIOS access not cached
3-14
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