Spi Interface - Quectel LTE-A Series Hardware Design

3.20. SPI Interface

EG060V-EA provides one SPI interface which only supports master mode with a maximum clock
frequency up to 50 MHz.
The following table shows the pin definition of SPI interface.
Table 24: Pin Definition of SPI Interface
Pin Name Pin No.
SPI_CS 166
SPI_MOSI 163
SPI_MISO 165
SPI_CLK 164
The figure below shows the timing of SPI interface. The related parameters of SPI timing are shown in the
following table.
Table 25: Parameters of SPI Interface Timing
Item Description
T SPI clock period
t(ch) SPI clock high level time
EG060V-EA_Hardware_Design
I/O Description
DO SPI chip select
DO SPI master-out
DI SPI master-in
DO SPI clock
T
SPI_CS_N
1
SPI_CLK
MSB
SPI_MOSI
t(mov)
SPI_MISO
Figure 28: SPI Interface Timing
EG060V-EA Hardware Design
t(ch) t(cl)
2 3 4
t(mis)
t(mih)
Min. Typ.
20.0 -
9.0 -
LTE-A Module Series
Comment
1.8 V power domain.
If unused, keep them open.
Max. Unit
- ns
- ns
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