Quectel LTE-A Series Hardware Design page 24
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- Hardware design (111 pages) ,
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- Hardware design (88 pages)
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2)
SPI Interface
Pin Name
Pin No.
SPI_CS
166
SPI_CLK
164
SPI_MOSI
163
SPI_MISO
165
PCIe Interface*
Pin Name
Pin No.
PCIE_REFCLK_
179
P
PCIE_REFCLK_
180
M
PCIE_TX_M
182
PCIE_TX_P
183
PCIE_RX_M
185
PCIE_RX_P
186
PCIE_CLKREQ
188
_N
PCIE_RST_N
189
PCIE_WAKE_N 190
EG060V-EA_Hardware_Design
I/O
Description
DO
SPI chip select
DO
SPI clock
DO
SPI master-out
DI
SPI master-in
I/O
Description
PCIe reference
AO
clock (+)
PCIe reference
AO
clock (-)
AO
PCIe transmit (-)
AO
PCIe receive (+)
AI
PCIe receive (-)
AI
PCIe receive (+)
IO
PCIe clock request
IO
PCIe reset
IO
PCIe wake up
LTE-A Module Series
EG060V-EA Hardware Design
DC Characteristics Comment
V
max = 0.45 V
1.8 V power domain.
OL
V
min = 1.35 V
If unused, keep it open.
OH
V
max = 0.45 V
1.8 V power domain.
OL
V
min = 1.35 V
If unused, keep it open.
OH
V
max = 0.45 V
1.8 V power domain.
OL
V
min = 1.35 V
If unused, keep it open.
OH
V
min = -0.3 V
IL
V
max = 0.6 V
1.8 V power domain.
IL
V
min = 1.2 V
If unused, keep it open.
IH
V
max = 2.0 V
IH
DC Characteristics Comment
If unused, keep it
open.
If unused, keep it
open.
If unused, keep it
open.
If unused, keep it
open.
If unused, keep it
open.
If unused, keep it
open.
V
max = 0.45 V
In master mode, it is an
OL
V
min = 1.35 V
input signal.
OH
V
min = -0.3 V
In slave mode, it is an
IL
V
max = 0.6 V
output signal.
IL
V
min = 1.2 V
If unused, keep it
IH
V
max = 2.0 V
open.
IH
V
max = 0.45 V
In master mode, it is an
OL
V
min = 1.35 V
output signal.
OH
V
min = -0.3 V
In slave mode, it is an
IL
V
max = 0.6 V
input signal.
IL
V
min = 1.2 V
If unused, keep it
IH
V
max = 2.0 V
open.
IH
V
max = 0.45 V
In master mode, it is an
OL
V
min = 1.35 V
input signal.
OH
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