Quectel LTE-A Series Hardware Design page 23

ADC Interfaces
Pin Name Pin No.
ADC0 173
ADC1 175
PCM and I2C Interfaces
Pin Name Pin No.
PCM_DIN 66
PCM_DOUT 68
PCM_SYNC 65
PCM_CLK 67
I2C_SCL 43
I2C_SDA 42
EG060V-EA_Hardware_Design
I/O Description
General-purpose
AI
ADC interface
General-purpose
AI
ADC interface
I/O Description
DI PCM data input
DO PCM data output
PCM data frame
IO
sync
IO PCM clock
I2C serial clock (for
OD
external codec)
I2C serial data (for
OD
external codec)
LTE-A Module Series
EG060V-EA Hardware Design
open.
DC Characteristics Comment
Voltage range: If unused, keep it
0 to 1.4 V open.
Voltage range: If unused, keep it
0 to 1.4 V open.
DC Characteristics Comment
V min = -0.3 V
IL
1.8 V power domain.
V max = 0.6 V
IL
If unused, keep it
V min = 1.2 V
IH
open.
V max = 2.0 V
IH
1.8 V power domain.
V max = 0.45 V
OL
If unused, keep it
V min = 1.35 V
OH
open.
V max = 0.45 V
1.8 V power domain. In
OL
master mode, it is an
V min = 1.35 V
OH
output signal. In slave
V min = -0.3 V
IL
mode, it is an input
V max = 0.6 V
IL
signal.
V min = 1.2 V
If unused, keep it
IH
open.
V max = 2.0 V
IH
1.8 V power domain. In
V max = 0.45 V
OL
master mode, it is an
V min = 1.35 V
OH
output signal. In slave
V min = -0.3 V
IL
mode, it is an input
V max = 0.6 V
signal.
IL
If unused, keep it
V min = 1.2 V
IH
open.
V max = 2.0 V
IH
An external pull-up
resistor is required.
1.8 V power domain 1.8 V only.
If unused, keep it
open.
An external pull-up
resistor is required.
1.8 V power domain 1.8 V only.
If unused, keep it
open.
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