Timing Example Of Ordinary (Non-Multiplexed) Bus - Fujitsu MB88121 Application Note

3.1.3.4 Timing example of ordinary (non-multiplexed) bus

Using the settings above the timing should look like following figure:
An example under the condition ACR_TYP[3:0]=3 and AWR=0x2008 is shown below.
Note:
•
The basic access cycle includes two clock cycles
•
AS
is asserted for one cycle in the bus access start cycle. The usage of pin ASX is
not necessary for MB88121B in the non-multiplexed mode.
•
AWR_W02=0,
•
RD WR
and
RD
assertion of
occurs after the wait cycle is finished (register AWR bit W15-W12).
•
AWR_W00=0,
•
For read access, data is read at the rising edge of the clock signal MCLK only when
the wait cycle is finished.
•
For write access, data output starts when
MCU-AN-300016-E-V10
Interfacing MB91460 TO MB88121
Chapter 3 Software
Figure 3-5 Timing example of the non-multiplexed mode
CS
is asserted at the same time when
are asserted at the second cycle of the bus access. If AWR_W01=1,
WR
and will be one cycle delayed after
CS
is negated direct after the bus cycle ends (
AS
WR
is asserted.
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is asserted.
CS
is asserted. Negation
RD WR
/ are negated).