Motorola M68060 User Manual page 88

$76543210 =
0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 1 X X X X X X X X X X X X X
TABLE ENTRY # =
ADDRESS OFFSET =
SRP
Figure 4-15. Translation Table with Nonresident Tables
4.2.5 Table Search Accesses
Table search accesses bypass the data cache. No allocation is done and no cache search
is performed. Translation tables must not be placed in copyback space, since the normal
accesses which build the translation tables would be cached and not written to external
memory, but the processor only uses tables in external memory.
During a table search, the U- and M-bits of the table descriptors are examined. For any
access, if the U-bit is not set, the processor sets it using a complete read-modify-write
sequence with the LOCK pin asserted. LOCK is asserted in this case to avoid loss of the
status in certain multiprocessor applications which share translation tables. For a write
access, if the M-bit in the page descriptor is not set, and if the page is not write-protected
(W = 0) and the access is not a supervisor violation (for user accesses, the S-bit of the page
descriptor must be clear), then the M-bit is set using a simple write. The U- and M-bits are
MOTOROLA
ROOT INDEX POINTER INDEX
$15
$3B
$54
$EC
SUPERVISOR
TABLE $00
NONRESIDENT
(PAGED OR
UNALLOCATED)
UDT = INVALID
UDT = INVALID
$3B UDT = RESIDENT
UDT = INVALID
UDT = INVALID
NONRESIDENT
(PAGED OR
UNALLOCATED)
ROOT-LEVEL
TABLES
M68060 USER'S MANUAL
LOGICAL ADDRESS
PAGE INDEX
$01
$04
TABLE $00
NONRESIDENT
(PAGED OR
UNALLOCATED)
TABLE $3B
UDT = INVALID
UDT = INVALID
$15 UDT = RESIDENT
UDT = INVALID
UDT = INVALID
TABLE $7F
NONRESIDENT
(PAGED OR
UNALLOCATED)
POINTER-LEVEL
TABLES
Memory Management Unit
PAGE OFFSET
TABLE $00
NONRESIDENT
(PAGED OR
UNALLOCATED)
TABLE $15
$01
FRAME ADDRESS
TABLE $1F
NONRESIDENT
(PAGED OR
UNALLOCATED)
PAGE-LEVEL
TABLES
4-19