Motorola M68060 User Manual page 347

12.7 INPUT AC TIMING SPECIFICATIONS (V
Num Characteristic
15 Data-In Valid to BCLK (Setup)
16 BCLK to Data-In Invalid (Hold)
BCLK to Data-In High Impedance
17
(Read Followed by Write)
22a TA, Valid to BCLK (Setup)
22b TEA Valid to BCLK (Setup)
22c TCI Valid to BCLK (Setup)
22d TBI Valid to BCLK (Setup)
22e TRA Valid to BCLK (Setup)
BCLK to TA, TEA, TCI, TBI, TRA Invalid
23
(Hold)
24 AVEC Valid to BCLK (Setup)
25 BCLK to AVEC Invalid (Hold)
41a BB Valid to BCLK (Setup)
41b BG Valid to BCLK (Setup)
41c CDIS, MDIS Valid to BCLK (Setup)
41d IPL » Valid to CLK (Setup)
41e BTT Valid to BCLK (Setup)
41f BGR Valid to BCLK (Setup)
42a BCLK to BB Invalid (Hold)
42b BCLK to BG Invalid (Hold)
42c BCLK to CDIS, MDIS Invalid (Hold)
42d CLK to IPLx Invalid (Hold)
42e BCLK to BTT Invalid (Hold)
42f BCLK to BGR Invalid (Hold)
44a Address Valid to BCLK (Setup)
44c TT1 Valid to BCLK (Setup)
44e SNOOP Valid to BCLK (Setup)
45a BCLK to Address Invalid (Hold)
45c BCLK to TT1 Invalid (Hold)
45e BCLK to SNOOP Invalid (Hold)
46 TS Valid to BCLK (Setup)
47 BCLK to TS Invalid (Hold)
BCLK to BB in High Impedance
49
(MC68060 Assumes Bus Mastership)
51 RSTI Valid to BCLK
52 BCLK to RSTI Invalid (hold)
53 Mode Select Setup to BCLK (RSTI Asserted)
BCLK to Mode Selects Invalid (RSTI Assert-
54
ed)
64 CLA Valid to BCLK (Setup)
65 BCLK to CLA Invalid (Hold)
NOTE:
BCLK is not a pin signal name. It is a virtual bus clock where the BCLK rising edge coincides with that of CLK when
CLKEN is asserted. The BCLK falling edge is insignificant. An input timing reference to BCLK means that the specific
input transitions only on rising CLK edges when CLKEN is asserted. A timing reference to CLK means that the input
may transition off the rising CLK edge, regardless of CLKEN state.
MOTOROLA
50 MHz
Min Max
2 Ñ
2 Ñ
Ñ 11
10 Ñ
10 Ñ
10 Ñ
10 Ñ
10 Ñ
2 Ñ
10 Ñ
2 Ñ
10 Ñ
10 Ñ
10 Ñ
2 Ñ
10 Ñ
10 Ñ
2 Ñ
2 Ñ
2 Ñ
2 Ñ
2 Ñ
2 Ñ
2 Ñ
10 Ñ
10 Ñ
2 Ñ
2 Ñ
2 Ñ
10 Ñ
2 Ñ
Ñ 3
2 Ñ
2 Ñ
10 Ñ
2 Ñ
10 Ñ
2 Ñ
M68060 USERÕS MANUAL
Electrical and Thermal Characteristics
= 3.3 V ± 5%)
CC
66 MHz 75 MHz
Min Max Min.
2 Ñ 2
2 Ñ 2
Ñ 9 Ñ
7 Ñ 6.2
7 Ñ 6.2
7 Ñ 6.2
7 Ñ 6.2
7 Ñ 6.2
2 Ñ 2
7 Ñ 6.2
2 Ñ 2
7 Ñ 6.2
7 Ñ 6.2
7 Ñ 6.2
2 Ñ 2
7 Ñ 6.2
7 Ñ 6.2
2 Ñ 2
2 Ñ 2
2 Ñ 2
2 Ñ 2
2 Ñ 2
2 Ñ 2
1 Ñ 2
7 Ñ 6.2
7 Ñ 6.2
2 Ñ 2
2 Ñ 2
2 Ñ 2
7 Ñ 6.2
2 Ñ 2
Ñ 3 Ñ
2 Ñ 2
2 Ñ 2
7 Ñ 6.2
2 Ñ 2
7 Ñ 6.2
2 Ñ 2
Unit
Max.
Ñ nS
Ñ nS
8 nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
3 nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
Ñ nS
12-5