Motorola M68060 User Manual page 26

Introduction
unit and the operand execution units. Fixed format instructions are dispatched to dual four-
stage pipelined RISC operand execution engines where they are then executed.
The branch cache also plays a major role in achieving the high performance levels of the
MC68060. It has been implemented such that most branches are executed in zero cycles.
Using a technique known as branch folding, the branch cache allows the instruction fetch
pipeline to detect and change the instruction prefetch stream before the change of flow
affects the instruction execution engines, minimizing the need for pipeline refill.
In addition to substantial cost and performance benefits, the MC68060 also offers advan-
tages in power consumption and power management. The MC68060 automatically mini-
mizes power dissipation by using a fully-static design, dynamic power management, and
low-voltage operation. It automatically powers-down internal functional blocks that are not
needed on a clock-by-clock basis. Explicitly the MC68060 power consumption can be con-
trolled from the operating system. Although the MC68060 operates at a lower operating volt-
age, it directly interfaces to both 3-V and 5-V peripherals and logic.
Complete code compatibility with the M68000 family allows the designer to draw on existing
code and past experience to bring products to market quickly. There is also a broad base of
established development tools, including real-time kernels, operating systems, languages,
and applications, to assist in product design. The functionality provided by the MC68060
makes it the ideal choice for a range of high-performance embedded applications and com-
puting applications. With M68000 family code compatibility, the MC68060 provides a range
of upgrade opportunities to virtually any existing MC68040 application.
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