Motorola M68060 User Manual page 61

Hex PST4 PST3
$00 0 0
$01 0 0
$02 0 0
$03 0 0
$04 0 0
$05 0 0
$06 0 0
$07 0 0
$08 0 1
$09 0 1
$0A 0 1
$0B 0 1
$0C 0 1
$0D 0 1
$0E 0 1
$0F 0 1
$10 1 0
$11 1 0
$12 1 0
$13 1 0
$14 1 0
$15 1 0
$16 1 0
$17 1 0
$18 1 1
$19 1 1
$1A 1 1
$1B 1 1
$1C 1 1
$1D 1 1
$1E 1 1
$1F 1 1
2.10.2 MC68060 Processor Clock (CLK)
CLK is the synchronous clock of the MC68060. This signal is used internally to clock or
sequence the internal logic of the MC68060 processor and is qualified with CLKEN to clock
all external bus signals.
Since the MC68060 is designed for static operation, CLK can be gated off to lower power
dissipation (e.g., during low-power stopped states). Refer to Section 7 Bus Operation for
more information on low-power stopped states.
2.10.3 Clock Enable (CLKEN)
This input signal is a qualifier for the MC68060 processor clock (CLK) and is provided to sup-
port lower bus frequency MC68060 designs. The internal MC68060 bus interface controller
will sample, assert, negate, or three-state signals (except for BB and TIP which can three-
MOTOROLA
Table 2-7. PSTx Encoding
PST2 PST1 PST0
0 0 0 Continue Execution in User Mode
0 0 1 Complete 1 Instruction in User Mode
0 1 0 Complete 2 Instructions in User Mode
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0 Emulator Mode Entry Exception Processing
0 0 1 Complete Not Taken Branch in User Mode
0 1 0 Complete Not Taken Branch Plus 1 Instruction in User Mode
0 1 1 IED Cycle of Branch to Vector, Emulator Entry Exception
1 0 0
1 0 1 Complete Taken Branch in User Mode
1 1 0 Complete Taken Branch Plus 1 Instruction in User Mode
1 1 1 Complete Taken Branch Plus 2 Instructions in User Mode
0 0 0 Continue Execution in Supervisor Mode
0 0 1 Complete 1 Instruction in Supervisor Mode
0 1 0 Complete 2 Instructions in Supervisor Mode
0 1 1
1 0 0
1 0 1 Complete RTE Instruction in Supervisor Mode
1 1 0 Low-Power Stopped State; Waiting for an Interrupt or Reset
1 1 1 MC68060 Is Stopped Waiting for an Interrupt
0 0 0 MC68060 Is Processing an Exception
0 0 1 Complete Not Taken Branch in Supervisor Mode
0 1 0 Complete Not Taken Branch Plus 1 Instruction in Supervisor Mode
0 1 1 IED Cycle of Branch to Vector, Exception Processing
1 0 0 MC68060 Is Halted
1 0 1 Complete Taken Branch in Supervisor Mode
1 1 0 Complete Taken Branch Plus 1 Instruction in Supervisor Mode
1 1 1 Complete Taken Branch Plus 2 Instructions in Supervisor Mode
M68060 USER'S MANUAL
Signal Description
Internal Processor Status
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