Motorola M68060 User Manual page 346

Electrical and Thermal Characteristics
12.6 OUTPUT AC TIMING SPECIFICATIONS (V
Num Characteristic
BCLK to Address CIOUT, LOCK,
LOCKE, R/W, SIZx, TLN, TMx,
4
11
TTx, UPAx, BSx Valid (signal pre-
driven)
BCLK to Address CIOUT, LOCK,
LOCKE, R/W, SIZx, TLN, TMx,
4
11a
TTx, UPAx, BSx Valid (signal from
three-state)
BCLK or CLK to Output Invalid
12
(Output Hold)
13 BCLK to TS Valid
14 BCLK to TIP Valid
18 BCLK to Data Out Valid
BCLK to Data Out Invalid (Output
19
Hold)
21 BCLK to Data-Out High Impedance
BCLK to Address, CIOUT, LOCK,
LOCKE, R/W, SIZx, TS, TLNx,
38
TMx, TTx, UPAx, BSx High Imped-
ance
39 CLK to BB, TIP High Impedance
BCLK to BR, BB Valid (Signal Pre-
4
40
driven)
BCLK to BB Valid (signal from
4
40a
three-state)
5
CLK to IPEND, PSTx, RSTO Valid
50
57 BCLK to SAS Valid
58 BCLK to SAS Invalid (Output Hold)
59 BCLK to SAS High Impedance
60 BCLK to TS Invalid (Output Hold)
61 BCLK to BTT Valid
62 BCLK to BTT Invalid (Output Hold)
63 BCLK to BTT High Impedance
NOTES:
1. Output timing is measured at the pin, assuming a capacitive load of 50 pF. A maximum load of 130 pF may be used,
however. Characterization indicates that at 130 pF loads, output propagation delays are modified as follows: 50 MHz,
Pad at V , multiply prop delay by 1.4; 50 MHz, Pad at 5.5 V, multiply prop delay by 1.6; 66 MHz, Pad at V
CC
prop delay by 1.3; 66 MHz, pad at 5.5 V, multiply prop delay by 1.4. Exceeding the 130-pF limit on any pin may affect
long-term reliability and Motorola does not guarantee proper operation.
2. In a mixed supply system where the processor drives chips operating with 5-volt supply, the ÒPad Starts at 5.5 VÓ
column should be used, as it is possible that a three-state pin is at 5.5 volts when the processor begins to drive it.
For a non three-state pin driven by the processor or a homogeneous 3.3-volt system, the ÒPad Starts at VccÓ column
must be used. This note does not apply to spec numbers 11, 11a, 40, and 40a. Refer to Note 5 for these specs.
3. BCLK is not a pin signal name. It is a virtual bus clock where the BCLK rising edge coincides with that of CLK when
CLKEN is asserted. The BCLK falling edge is insignificant. An output timing reference to BCLK means that the spe-
cific output transitions only on rising CLK edges when CLKEN is asserted. A timing reference to CLK means that the
output may transition off the rising CLK edge, regardless of CLKEN state.
4. When the processor drives these signals from a three-stated condition, use spec 11a or 40a. Use the ÒPad Starts at
V Ó column or ÒPad Starts at 5.5 VÓ column as appropriate. Once these signals are driven, subsequent transitions
CC
are defined by spec 11 or 40. The ÒPad Starts at 5.5 VÓ column has no entry for specs 11 and 40, since the processor
only drives up to the V
CC
5. ÒPad Starts at 5.5 V" does not apply since these signals are always driven.
12-4
50 MHz
Pad
Starts
2
at 5.5 V
Min Max Min Max Min Max Min Max Min Max Min Max
Ñ Ñ
2 15.4
2 Ð
2 14.4
2 15.4
2 13.5
2 Ð
Ñ 12
Ñ 12
Ñ 12
Ñ Ñ
2 15.4
Ñ Ñ
2 15.4
2 Ð
Ñ 12
2 Ð
2 15.4
2 Ð
Ñ 12
level. BR is never three-stated by the processor, and therefore, spec 40a does not apply.
M68060 USERÕS MANUAL
= 3.3 V ± 5%)
CC
66 MHz
Pad Pad
Pad
Starts Starts
Starts
2
2
at V at V
at 5.5 V
CC
2 12.6 Ñ Ñ 2
2 13.5 2 11.8 2
2 Ð 2 Ð 2
2 12.3 2 10.9 2
2 13.5 2 11.8 2
2 13.5 2 10.4 2
2 Ð 2 Ð 2
Ñ 12 Ñ 10 Ñ
Ñ 12 Ñ 10 Ñ
Ñ 12 Ñ 10 Ñ
2 12.6 Ñ Ñ 2
2 13.5 2 11.8 2
2 13.5 Ñ Ñ 2
2 13.5 2 11.8 2
2 Ð 2 Ð 2
Ñ 12 Ñ 10 Ñ
2 Ð 2 Ð 2
2 13.5 2 11.8 2
2 Ð 2 Ð 2
Ñ 12 Ñ 10 Ñ
75 MHz
Pad
Pad
Starts
Starts
2
2
at V
at 5.5 V
CC CC
9.9 Ñ Ñ 1.5 8.8
10.4 1.5 10.5 1.5 9.2
Ð 1.5 Ð 1.5 Ð
9.5 1.5 9.7 1.5 8.4
10.4 1.5 10.5 1.5 9.2
10.4 1.5 9.2 1.5 9.2
Ð 1.5 Ð 1.5 Ð
10 Ñ 8.9 Ñ 8.9
10 Ñ 8.9 Ñ 8.9
10 Ñ 8.9 Ñ 8.9
9.9 Ñ Ñ 1.5 8.8
10.4 1.5 10.5 1.5 9.2
10.4 Ñ Ñ 1.5 9.2
10.4 1.5 10.5 1.5 9.2
Ð 1.5 Ð 1.5 Ð
10 Ñ 8.9 Ñ 8.9
Ð 1.5 Ð 1.5 Ð
10.4 1.5 10.5 1.5 9.2
Ð 1.5 Ð 1.5 Ð
10 Ñ 8.9 Ñ 8.9
, multiply
CC
Unit
2
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
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