Motorola M68060 User Manual page 401

CPUSH
Operation: If Supervisor State, Then
If Data Cache, Then
Endif
If Instruction Cache, Then
Endif
Endif
Else TRAP
Assembler
Syntax: CPUSHL<caches>,(An)
CPUSHP<caches>,(An)
CPUSHA<caches>
Where <caches> specifies the instruction cache, data
cache, both caches, or neither cache.
Attributes: Unsized
Description: Pushes and possibly invalidates selected cache lines. The data cache,
instruction cache, both caches, or neither cache can be specified. When the data
cache is specified, the selected data cache lines are first pushed to memory (if they
contain dirty data) and then invalidated if the DPI bit of the CACR is cleared. Otherwise,
the selected data cache lines remain valid. Selected instruction cache lines are invali-
dated. The CACR is accessed via the MOVEC instruction.
Specific cache lines can be selected in three ways:
1. CPUSHL pushes and possibly invalidates the cache line (if any) matching the
physical address in the specified address register.
2. CPUSHP pushes and possibly invalidates the cache lines (if any) matching the
physical memory page in the specified address register. For example, if 4K-byte
page sizes are selected and An contains $12345000, all cache lines matching
page $12345000 are selected.
3. CPUSHA pushes and possibly invalidates all cache entries.
MOTOROLA
Push and Possibly Invalidate Cache Line
(MC68060, MC68LC060, MC68EC060)
Push Selected Dirty Data Cache Lines
If DPI bit of CACR = 0, Then
Invalidate Selected Cache Lines
Endif
Invalidate Selected Cache lines
M68060 USER'S MANUAL
MC68060 Instructions
CPUSH
D-11