Starting The Superclock-2 Module - Xilinx Virtex-7 FPGA VC7215 Getting Started Manual

Chapter 1: VC7215 IBERT Getting Started Guide

Starting the SuperClock-2 Module

The IBERT demonstration designs use an integrated VIO core to control the clocks on the
SuperClock-2 module. The SuperClock-2 module features two clock-source components:
•
•
Outputs from either device can be used to drive the transceiver reference clocks.
To start the SuperClock-2 module:
1.
X-Ref Target - Figure 1-13
18
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An always-on Si570 crystal oscillator
An Si5368 jitter-attenuating clock multiplier.
The Vivado Design Suite Hardware Manager window shows the System ACE™ SD
Controller and the XC7VX690T device. The XC7VX690T_1 device is reported as
programmed. In the Hardware Device Properties window, enter the file path to the
Q115 probes file (vc7215_ibert_q115_debug_nets.ltx) in the extracted IBERT
files from the SD card (Figure
Figure 1-13: Adding the Probes File
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1-13).
UG970 (v7.0) November 24, 2014
VC7215 Getting Started Guide