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X-Ref Target - Figure 1-7
Table 1-4
Table 1-4: JTAG Isolation Jumpers
200 MHz 2.5V LVDS Oscillator
[Figure
The SP623 board has one 2.5V LVDS differential 200 MHz oscillator (U7) connected to the
FPGA global clock inputs.
The 200 MHz differential clock is enabled by placing two shunts (P, N) across J188 header
pins 1 – 3 and 2 – 4 (LVDS).
Table 1-5: LVDS Oscillator Global Clock Connections
SuperClock-2 Module
[Figure
The SuperClock-2 module connects to the clock module interface connector (J32) and
provides a programmable, low-noise clock source for the SP623 board. The clock module
maps to FPGA I/O by way of 24 control pins, 3 LVDS pairs, 1 regional clock pair, and 1
reset pin.
The SP623 board also supplies VCC5, VCC3V3, VCC2V5, and VCCO input power to the
clock module interface.
SP623 Board User Guide
UG751 (v1.0) May 22, 2010
U1
FPGA
Figure 1-7: JTAG Isolation Jumpers
indicates the FPGA pin name associated with each jumper.
Reference Designator
J22
J23
J195
J196
1-2, callout 10]
FPGA Pin
V23
IO_LVDS_CLK_P
W24
IO_LVDS_CLK_N
1-2, callout 11]
Table 1-6
shows the FPGA I/O mapping for the SuperClock-2 module interface.
www.xilinx.com
J196
TCK
J195
TDO
J23
TDI
J22
TMS
FPGA Pin Name
TMS
TDI
TDO
TCK
Table 1-5
lists the FPGA pin connections to the LVDS oscillator.
Net Name
U7 Pin
Detailed Description
U25
System ACE
Controller
CFGTCK
CFGTDI
CFGTDO
CFGTMS
UG751_c1_07_050110
4
5
17
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