Superclock-2 Frequency Table - Xilinx Virtex-7 FPGA VC7222 Getting Started Manual

In Case of RX Bit Errors
If there are initial bit errors after linking, or as a result of changing the TX or RX pattern, click
the respective BERT Reset button to zero the count.
Additional information on the Vivado Design Suite and IBERT core can be found in Vivado
Design Suite User Guide: Programming and Debugging (UG908)
Integrated Bit Error Ratio Tester (IBERT) for 7 Series GTX Transceivers Product Guide for
Vivado Design Suite (PG132)
Closing the IBERT Demonstration
To stop the IBERT demonstration:
1. Close the Vivado Design Suite by selecting File > Exit.
2. Place the main power switch SW1 in the OFF position.

SuperClock-2 Frequency Table

Table 1-2 lists the addresses for the frequencies that are programmed into the SuperClock-2
read-only memory (ROM).
Table 1-2: Si570 and Si5368 Frequency Table
Address Protocol
0 100GE/40GE/10GE
1 Aurora
2 Aurora
3 Aurora
4 Aurora
5 CE111
6 CPRI™
7 CPRI
8 CPRI
9 CPRI
10 CPRI
11 Display Port
12 Display Port
13 Display Port
VC7222 IBERT Getting Started Guide
UG971 (Vivado Design Suite v2015.1) April 27, 2015
[Ref 4].
Frequency
Address Protocol
(MHz)
161.30 30 OBSAI
81.25 31 OBSAI
162.5 32 OC-48
325 33 OC-48
650 34 OC-48
173.37 35 OC-48
61.44 36 OC-48
122.88 37 OTU-1
153.63 38 OTU-1
245.76 39 OTU-1
491.52 40 OTU-1
67.5 41 OTU-2
81 42 OTU-2
135 43 OTU-3
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Chapter 1: VC7222 IBERT Getting Started Guide
[Ref 3]
Frequency Address Protocol Frequency
(MHz)
307.2 60
614.4 61
19.44 62
77.76 63
155.52 64
311.04 65
622.08 66
166.629 67
333.257 68
666.514 69
666.75 70
167.33 71
669.31 72
168.05 73
and in LogiCORE IP
(MHz)
XAUI 156.25
XAUI 312.5
XAUI 625
Generic 66.667
Generic 133.333
Generic 166.667
Generic 266.667
Generic 333.333
Generic 533.333
Generic 644
Generic 666.667
Generic 205
Generic 210
Generic 215
43
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