Sdac Interrupt Enable Register - Epson S1C31D50 Technical Manual

SDAC Interrupt Enable Register

Register name Bit
SDACINTE 15–8 –
7–2 –
1
0
Bits 15–2 Reserved
Bit 1 ERRIE
Bit 0 DATREQIE
These bits enable SDAC interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
The following shows the correspondence between the bit and interrupt:
SDACINTE.ERRIE bit:
SDACINTE.DATREQIE bit: Data request interrupt
Note: This register is used by the HWP. Do not write any data to this register while the HWP operation
is enabled (HWPCTL.HWPEN bit = 1).
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Bit name Initial
0x00
0x00
ERRIE 0
DATREQIE 0
Error occurrence interrupt
Seiko Epson Corporation
21 HW Processor (HWP) and Sound Output
Reset R/W
– R –
– R
H0 R/W
H0 R/W
Remarks
21-29