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7 I/O PORTS (PPORT)
Peripheral I/O function 0 I/O control
Peripheral I/O function 1 I/O control
Peripheral I/O function 2 I/O control
Peripheral I/O function 3 I/O control
Clock
generator
Key-entry
reset signal
System reset
controller
CPU core
7.2 I/O Cell Structure and Functions
Figure 7.2.1 shows the I/O cell Configuration.
Pull-up/down
Control signal
Input signal
Input control signal
Output signal
Output control signal
Analog signal
Analog control signal
Over voltage tolerant fail-safe type I/O cell
Refer to "Pin Descriptions" in the "Overview" chapter for the cell type, either the over voltage tolerant fail-safe
type I/O cell or the standard I/O cell, included in each port.
7.2.1 Schmitt Input
The input functions are all configured with the Schmitt interface level. When a port is set to input disable status
(PPORTPxIOEN.PxIENy bit = 0), unnecessary current is not consumed if the Pxy pin is placed into floating status.
7-2
PPORT
Pxy
Pxy
Pxy
PxSELy
PxyMUX[1:0]
PxOUTy
PxOENy
PxIENy
PxPDPUy
PxRENy
PxCHATENy
CLKSRC[1:0]
PxINy
CLKDIV[3:0]
DBRUN
CLK_PPORT
Key-entry
PxEDGEy
reset control
PxINT
circuit
PxIFy
KRSTCFG[1:0]
PxIEy
Figure 7.1.1 PPORT Configuration
V
DD
Pull-up/down
control
R
/
V
INU
SS
R
IND
V
DD
∗ No diode is
connected at
V
the V
side.
DD
DD
Analog signal
V
control
SS
Figure 7.2.1 I/O Cell Configuration
Seiko Epson Corporation
GPIO/
peripheral I/O
GPIO function
function
switching
General-purpose
circuit
I/O control
Chattering
filter
Interrupt
control circuit
Exist only in the ports that supports the interrupt function.
Pull-up/down
Control signal
Input signal
Input control signal
Output signal
Pxy
Output control signal
Analog signal
Analog control signal
Standard I/O cell
I/O cell
control signal
Output signal
I/O cell
Input signal
V
DD
Pull-up/down
control
R
/
V
INU
SS
R
IND
V
DD
V
DD
V
DD
Analog signal
V
control
SS
S1C31D50/D51 TECHNICAL MANUAL
(Rev. 2.00)
Pxy
Pxy
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