Overview; Hardware Description; System Architecture - Huawei NE40E-X1 Hardware Description

HUAWEI NE40E-X1 & NE40E-X2 Universal Service
Router

Hardware Description

2.1 Overview

The NE40E-X2 is a high-end network device developed by Huawei. This device is based on the
VRP and applies to the access, convergence, and transmission of Metro Ethernet services.
The NE40E-X2 has great capabilities in network access, Layer 2 switching, and EoMPLS
transmission, and supports a wide range of high-speed and low-speed interfaces. Hence, the
NE40E-X2 supports triple-play of voice, video, and data services and can bear 2G/3G/LTE
services simultaneously. The NE40E-X2 can be deployed together with Huawei NE, CX, and
ME series products to build a Metro Ethernet network with a clear hierarchy and offer extensive
services. This chapter provides an overview of the hardware of the NE40E-X2.
2.1.1 Hardware Description
By adopting a centralized routing engine and NP forwarding structure, the NE40E-X2 has a
great capacity and can provide extensive services.
The NE40E-X2 adopts an integrated chassis that can be installed independently. The main parts
of the NE40E-X2 such as MPUs, NPUs, PICs, fan modules, and PSUs are hot-swappable.
Figure 2-1
and eight slots for PICs. The network process unit on the NE40E-X2 is NPUI-20. All the PICs
perform data switching through the NPUI-20. The NPUI-20 has a bidirectional processing
capability of up to 20 Gbit/s.
The maximum interface capacity of the NE40E-X2 is 75.2 Gbit/s.
Figure 2-1 Outline of the NE40E-X2

2.1.2 System Architecture

The logical architecture of the NE40E consists of the following planes: data plane, control and
management plane, and monitoring plane, as shown in
switches data packets quickly and smoothly; the control and management plane, as the core of
the system, controls and manages the system; the monitoring plane monitors the ambient
operating conditions.
Issue 02 (2011-09-10)
shows the outline of the NE40E-X2. The NE40E-X2 provides two slots for NPUs
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2 NE40E-X2 Hardware Description
Figure 2-2. The data plane processes and
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