Tft Board (4/8) (Xav-Ax200C2) - Sony XAV-AX200 Service Manual

2018/04/20 05:09:38 (GMT+09:00)
5-28. SCHEMATIC DIAGRAM - TFT Board (4/8) (XAV-AX200C2) -
1
TFT BOARD (4/8)
A
R238
[4] A_RMA0
R236
33R
[4] A_RMA1
R226
[4] A_RMA2
R229
33R
[4] A_RMA3
R231
[4] A_RMA4
R230
33R
[4] A_RMA5
R232
[4] A_RMA6
R203
33R
[4] A_RMA7
R233
[4] A_RMA8
R227
33R
[4] A_RMA9
R239
[4] A_RMA10
R235
33R
[4] A_RMA11
R237
B [4] A_RMA12
R228
33R
A_RMA13
[4]
R234
[4] A_RMA14
33R
R240
[4] A_RMA15
[4] A_RDQS0H
[4] A_RDQS0H#
[4] A_RDQS0L
[4] A_RDQS0L#
10R
R65
[4] A_RDQM0L
R66
[4] A_RDQM0H
RN13
[4] A_RWE
[4] A_RODT
[4] A_RCAS
[4] A_RRAS
10Rx4
C
R298
33R
[4] A_RRESET
R297
33R
[4] A_RBA2
R299
33R
[4] A_RBA1
R296
33R
[4] A_RBA0
D
M15
GND
M14
GND
M13
GND
M12
GND
M11
GND
M10
GND
M9
GND
M8
GND
M7
GND
L16
GND
L15
GND
L14
GND
E L13
GND
L12
GND
L11
GND
L10
GND
L9
GND
L8
GND
L7
GND
K15
GND
K14
GND
K13
GND
K12
GND
K11
GND
K10
GND
K9
GND
K8
GND
J14
GND
J13
GND
J12
GND
Y7
GND
Y4
GND
Y2
GND
W6
F
GND
XAV-AX200/AX200C2
2 3 4
A_RMD4
[4]
U1-A
[4] A_RMD6
T2
33R W8
A_A0 A_D0 A_RMD0 [4]
[4] A_RMD2
Y6 AB4
A_A1 A_D1 A_RMD1 [4]
33R M3 T1 [4] A_RMD0
A_A2 A_D2 A_RMD2 [4]
T3 AA5
A_D3 A_RMD3
A_A3 [4]
33R V4 R1
A_A4 A_D4 A_RMD4 [4]
[4] A_RMD11
R4 AA6
A_A5 A_D5 A_RMD5 [4]
33R W4 R2 [4] A_RMD13
A_A6 A_D6 A_RMD6 [4]
P4 AB5
A_A7 A_D7 A_RMD7 [4] [4] A_RMD9
33R Y3 AA3
A_A8 A_D8 A_RMD8 [4]
A_RMD15
[4]
M4 V1
A_A9 A_D9 A_RMD9 [4]
AA8 AA4
33R
A_A10 A_D10 A_RMD10 [4]
Y5 U1
A_A11 A_D11 A_RMD11 [4] [4] A_RMD12
33R W7 AB2
A_A12 A_D12 A_RMD12 [4]
[4] A_RMD8
N4 U2
A_A13 A_D13 A_RMD13
[4]
33R W5 AB3
[4] A_RMD14
A_A14 A_D14 A_RMD14 [4]
AB8 V2
A_A15 A_D15 A_RMD15 [4] [4] A_RMD10
AA2 U4
A_DQS1 A_VREF A_VREF
[4]
AB1 U3 C316
A_DQS1B A_PLL33 DDR_PLL33 [3]
104
W2 M5 [4] A_RMD1
DDR_1V5
A_DQS0 A_VDDQ [3,4]
Y1 N5
A_VDDQ A_RMD3
A_DQS0B [4]
AA1 P5
A_DM0 A_VDDQ
[4] A_RMD7
10R W1 R5
A_DM1 A_VDDQ
N1 T5 [4] A_RMD5
A_WE_B A_VDDQ
N2 U5
A_ODT A_VDDQ
P1 V5
A_CAS_B A_VDDQ
P2 V6
A_RAS_B A_VDDQ
P3 V7
A_RST_B A_VDDQ
M1 V8
A_BA2 A_VDDQ
[3,4]
V3 AB7
DDR_1V5
A_BA1 A_CKE A_RCKE [4]
M2 AB6
A_BA0 A_CK A_RCLK
[4]
AA7
A_CKB A_RCLK# [4]
AR1668
C26
10pF
AVDD33
[3]
PLL_VDD33
[3]
G12
PLLC_AVDD
[3]
G11
PLL_AVDD PLL_1V2
U12
VDD11 CORE_1V1
T15
[3,5]
VDD11
T12
VDD11
T11
VDD11
T10
VDD11
T9
VDD11
T8
VDD11
T7
VDD11
R15
VDD11
R14
VDD11
U1-G
R13
VDD11
AR1668
R12
VDD11
R7
VDD11
P7
VDD11
K17
VDD11
K16
VDD11
K7
VDD11
J16
VDD11
J15
VDD11
J11
VDD11
J10
VDD11
J7
VDD11
J9
VDD11
J8
VDD11
H15
VDD11
H14
VDD11
H13
VDD11
H12
VDD11
H11
VDD11
OTP_V25
C299
1uF
5 6
RN11
2 1
DDR_D4 [4]
[3,4]
4 3
DDR_D6 DDR_1V5
[4]
6 5
DDR_D2 [4]
8 7
DDR_D0 [4]
10Rx4
U2
RN15
DDR_D11
[4]
N3
DDR_D13 [4] [4] A_RMA0 A0
P7
[4] A_RMA1 A1
DDR_D9 [4]
P3
[4] A_RMA2 A2
DDR_D15 N2
[4]
[4] A_RMA3 A3
P8
10Rx4
[4] A_RMA4 A4
RN16
P2
A_RMA5 A5
[4]
DDR_D12 [4]
R8
[4] A_RMA6 A6
DDR_D8 [4] R2
[4] A_RMA7 A7
T8
DDR_D14
[4] [4] A_RMA8 A8
R3
[4] A_RMA9 A9
DDR_D10
[4]
L7
[4] A_RMA10 A10/AP
10Rx4
R7
RN17
[4] A_RMA11 A11
N7
DDR_D1 [4] [4] A_RMA12 A12
T3
[4] A_RMA13 A13
DDR_D3 [4]
T7
[4] A_RMA14 A14
DDR_D7
[4] M7
[4] A_RMA15 NC
VREFDQ
DDR_D5 [4]
D3
10Rx4 [4] A_RDQM0H DMU
E7
A_RDQM0L
[4] DML
C7
[4] A_RDQS0H DQSU
B7
[4] A_RDQS0H# DQSU#
F3
[4] A_RDQS0L DQSL
[3,4] G3
[4] A_RDQS0L# DQSL#
DDR_1V5
K1
[4] A_RODT ODT
R22
L2
CS#
10K M2
[4] A_RBA0 BA0
C28 C27 N8
[4] A_RBA1 BA1
NC
M3
[4] A_RBA2 BA2
104
[4]
[4] L3
[4] A_RWE WE#
A_VREF A_RVREF
J3
[4] A_RRAS RAS#
K3
[4] A_RCAS CAS#
C30 C29
104 104
[3,4]
[3,4]
DDR_1V5
DDR_1V5
C207
C194 C302
C282 C283 C284 C285 C286 C287 C288 C289 C290 C291
10uF 10uF 104
10uF 104 104 104 104 104 104 104 104 104
P ow er bypass cap. for V D D Q _15
51 51
7 8
[3,4]
DDR_1V5
E3
DDR_D0
DQ0 [4]
W632GG6KB-12I(x16) F7
DQ1 DDR_D1 [4]
F2
DQ2 DDR_D2 [4]
F8
DDR_D3 [4]
DQ3
H3
DQ4 DDR_D4 [4]
1 2 3 7 8 9
H8
DQ5 DDR_D5 [4]
A
G2
DDR_D6
VDDQ DQ13 DQ15 DQ12 VDDQ VSS DQ6 [4]
B
H7
DQ7 DDR_D7
[4]
VSSQ VDD VSS /DQSU DQ14 VSSQ
D7
C DQ8 DDR_D8 [4]
VDDQ DQ11 DQ9 DQSU DQ10 VDDQ C3
DDR_D9
DQ9 [4]
D
C8
VSSQ VDDQ DMU DQ8 VSSQ VDD DQ10 DDR_D10
[4]
E C2
DQ11 DDR_D11 [4]
VSS VSSQ DQ0 DML VSSQ VDDQ
A7
F DDR_D12
DQ12 [4]
VDDQ DQ2 DQSL DQ1 DQ3 VSSQ A2
DDR_D13
DQ13 [4]
G
B8
VSSQ DQ6 /DQSL VDD VSS VSSQ DQ14 DDR_D14 [4]
H A3
DQ15 DDR_D15 [4]
VDDQ DQ4 DQ7 DQ5 VDDQ
J
H1
NC VSS /RAS CK VSS NC
VREFDQ A_RVREF [4]
K
M8
ODT VDD /CAS /CK VDD CKE VREFCA
L
NC /CS /WE A10/AP ZQ NC
J7
M CK A_RCLK [4]
VSS BA0 BA2 NC VREFCA VSS K7
CK# A_RCLK# [4]
N
K9
VDD A3 A0 A12/BC# BA1 VDD CKE A_RCKE [4]
P
VSS A5 A2 A1 A4 VSS
T2
R RESET# A_RRESET [4]
VDD A7 A9 A11 A6 VDD L8
ZQ
T
VSS /RST A13 NC A8 VSS
J1
R23
NC
J9
NC
L1 240R/1%
NC
L9
NC
NOM. 2Gb
MAX. 4Gb
1. NT5CB128M16FP-DI -40 ~ 95
P ow er bypass cap. for V D D Q _15
C310
C303 C304 C305 C306 C309 C311 C312 C314 C315 C354 C355 C375
104 104 104 104 104 104 104 104 104 104 100P 100P 680P
XAV-AX200/AX200C2
Ver. 1.1
SYS SET