Arm926 Tightly Coupled Memories (Arm926_Tcm) - Siemens ERTEC 200P-2 Manual

'EDC_PARITY_EN' (see 2.3.10.9.22
the I-cache and I-tag, and 'D_CACHE_PAR_EN-Bit' the parity bits of the D-cache and D-
tag. After reset, both bits are set to '0' and the parity bits are disabled. The SW can set
these bits to '1' after cache initialization.

2.3.1.3.2 ARM926 Tightly Coupled Memories (ARM926_TCM)

The I-TCM and D-TCM are located in TCM_Block_926. The TCM configuration includes
2
256 KByteF for instruction and data TCM (I/D-TCM). The memory operates at the clock
rate of the processor, 125/250 MHz. The memory consists of segments of 64 KByte,
which can be assigned either to the instruction or to the data TCM. This results in a con-
figurable memory size of 0 – 256 KByte for the I-TCM with 256 – 0 KByte for the D-TCM.
After reset, the TCM926 configuration is 256 KByte D-TCM. The final setting is made
during booting by the boot loader (SW), in the SCRB register 'TCM926_Map' (see
2.3.10.9.22). After this reconfiguration, the boot loader must still display the TCM memo-
ries in the address range of the coprocessor interface (CP15 c9) (see 2.4.1 and 2.4.2).
Please note that I-TCM and D-TCM can only be displayed in the address range in incre-
n
ments of 2 . If, for example, a physical size of I-TCM = 192 KByte / D-TCM = 64 KByte
has been selected in 'TCM926_Map Register', ARM926 can only assign I-TCM an ad-
dress range of 256 KByte and D-TCM the required address range of 64 KByte. The val-
ues 256 KByte for I-TCM and 64 KByte for D-TCM are therefore to be read out in the
coprocessor interface of ARM926 (CP15 c9).
The SW must then not access the unassigned area / hole (I-TCM: 192 – 256 KByte). If
ARM926 accesses the unassigned area in the event of an error, either 'Invalid I-TCM926
Access Interrupt' (access to the I-TCM hole) or 'Invalid D-TCM926 Access Interrupt' (ac-
cess to the D-TCM hole) is triggered (see 2.3.2.14).
Unpredictable access to the I/D-TCM hole cannot be prevented by ARM926; 'Invalid I/D-
TCM926 Access Interrupt' is generated. The situation can be dealt with if the MMU de-
codes the hole and 'Invalid I/D-TCM926 Access Interrupt' is blocked. The MMU is not
deisgn for unpredictable access.
I-TCM and D-TCM are each assigned an address range of 256 KByte in implementation.
This covers all possible combinations of I-TCM and D-TCM. Once shown, the I-TCM is in
the ARM926 address range from 0x0000_0000h and the D-TCM from 0x0800_0000h.
More information on TCMs can be found in /7/ (see chapter 7.2).
Only ARM926 D-TCM can be accessed from the AHB. In the event of access to the un-
assigned D-TCM address range from an AHB master, access is prevented and a QVZ
interrupt is triggered (see 5.8.1).
AHB access to D-TCM is with the 'DMA-DTCM Access Controller'. The I-TCM is only
used by ARM926EJ-S and cannot by accessed by the AHB.
The I-TCM and D-TCM have an EDC code, which is assigned byte by byte (5 bits per
byte, 1-bit error, correctable; 2-bit error, detectable). If an error occurs during reading, the
cause of the error (I/D-TCM926-1B: 1-bit error corrected or I/D-TCM926-2B: 2-bit error
detected) is saved in the SCRB register 'EDC_EVENT' (see 2.3.10.9.22
'EDC_Event' IRQ48 is triggered (see 2.3.2.14
register to clear the error.
2
1 KByte is equal to 1024 bytes.
Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
). 'I_CACHE_PAR_EN-Bit' enables the parity bits of
X
). '0h' must be written to the EDC event
X
28
) and the interrupt
X
ERTEC 200P-2 Manual
Version 1.0