System Reliability; Electromagnetic Compatibility (Emc) - Siemens ERTEC 200P-2 Manual

General functions:
Internal clock generation (quartz oscillator, PLL)
Integrated boot ROM (8 KByte)
6 x timer
Watchdog
F-counter
GDMA controller
ARM926 interrupt controller
Test functions:
Boundary scan
The complete ERTEC 200P can be switched to external high impedance with a bound-
ary scan command.

1.2.1 System Reliability

A soft error rate of fewer than 1000 FIT at an altitude of 2000 m is required for the
complete ASIC. As the required SER cannot be achieved with the current level of RAM
complexity without additional error mechanisms, an EDC mechanism (Error Detection
and Correction) is in place for all more complex RAMs. The EDC circuit detects and
corrects 1-bit errors and detects but does not correct 2-bit errors.
Logically adjacent bits are located in the manufacturer's single port RAMs in physically
separate (different) words; 2-bit errors can therefore be corrected by the error correc-
tion in logically adjacent bits. RAMs with EDC can therefore be ignored for the soft
error rate. A more precise breakdown of FIT rates can be found in

1.2.2 Electromagnetic Compatibility (EMC)

The ERTEC 200P ASIC and the systems/devices implemented with it are designed for
EMC in accordance with EN61000-6-2 (Generic standards - Immunity) and EN61000-
6-4 (Generic standards - Emission standard).
These standards are the device standards for use in industrial environments. For com-
pliance with these device standards, however, the EMC of the individual integrated
circuits used (in particular immunity to interference in operation) is key.
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Technical data subject to change
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6.
ERTEC 200P-2 Manual
Version 1.0