Interrupts For Accesses To Missing Addresses; Confirmation Delay In The Memory Controller (Emc) Address Area; Table 9: Host Inta, Interrupt Sources - Siemens ERTEC 200P-2 Manual

IRQ Interrupt Name
no.
87 ETB_ACQCOM
P
Invalid I-
88
TCM926 Access
Invalid D-
89 TCM926
Access
90 ETB_FULL
91 Reserved
92 Reserved
93 Reserved
94 COMMRX926
95 COMMTX926
Type ET/R Edge triggered interrupt, on the rising edge.
Type ET/F Edge triggered interrupt, on the falling edge.
Type LT Level triggered interrupt.
Type *) This type is dependent on the selected mode of the module
Type **) This type is dependent on the external switch (ASIC-Pins). It can be ET/F or ET/R or LT, depending
on the external connection. Parameterization must be done depending on the request of the applica-
tion about the Host-ICU (see chapter 2.3.2.17).
Information:
The IRQ interrupt output of ARM-ICU (ICUIRQ_O) is inverted and connected to the inter-
rupt input (nIRQ) of ARM926EJ-S.
2.3.2.14.1

Interrupts for accesses to missing addresses

The QVZ units detect any access to missing addresses and generate a pulse with dura-
tion Tp = 2/125 MHz. This pulse must be processed in the Interrupt Controller as an
edge-triggered interrupt.
2.3.2.14.2

Confirmation delay in the Memory Controller (EMC) address area

Copyright © Siemens AG 2016. All rights reserved
Technical data subject to change
Ty- Signal
pe
ET/ ETB_ACQCOMP
R
ET/
R
ET/
R
ET/ ETB_FULL
R
-----
-----
-----
LT COMMRX926
LT COMMTX926

Table 9: Host INTA, Interrupt sources

68
Cause
modules
Combined Interrupt for
address mismatches in
modules
ARM926 has accessed an I-
TCM address gap
ARM926 has accessed a D-
TCM address gap
Trace overrun in trace buff-
er
Interrupt for Realltime De-
bugger (receive Buffer con-
tains data)
Interrupt for Realltime De-
bugger (transmit buffer is
empty)
Interrupt
source
ARM926
ARM926
ERTEC 200P-2 Manual
Version 1.0