Fpga Mezzanine Card Interface - Xilinx AC701 User Manual

Chapter 1: AC701 Evaluation Board Features
The default mode setting is M[2:0] = 001, which selects Master SPI flash memory at board
power-on.
Table 1-25: AC701 Board FPGA Configuration Modes
Master SPI flash memory
JTAG
See 7 Series FPGAs Configuration User Guide (UG470)
the 7 series FPGAs.

FPGA Mezzanine Card Interface

[Figure
The AC701 board supports the VITA 57.1 FPGA mezzanine card (FMC) specification by providing
high pin count (HPC) connector J30. HPC J30 is keyed so that a the mezzanine card faces away from
the AC701 board when connected.
Signaling speed ratings:
•
•
•
•
The Samtec connector system is rated for signaling speeds up to 9 GHz (18 Gb/s) based on a –3 dB
insertion loss point within a two-level signaling environment.
Connector type:
•
For more information about SEAF series connectors, go to the Samtec website
HPC Connector J30
[Figure
The 400-pin HPC connector defined by the FMC specification
for up to:
•
•
•
•
•
The connections between the HPC connector at J30 and FPGA U1
of this connectivity:
•
58
Send Feedback
Configuration Mode
1-2, callout 29]
Single-ended: 9 GHz (18 Gb/s)
Differential optimal vertical: 9 GHz (18 Gb/s)
Differential optimal horizontal: 16 GHz (32 Gb/s)
High density vertical: 7 GHz (15 Gb/s)
Samtec SEAF series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector
1-2, callout 29]
160 single-ended or 80 differential user-defined signals
10 GTP transceivers
2 GTP transceiver clocks
4 differential clocks
159 ground and 15 power connections
58 differential user defined pairs
• 34 LA pairs (LA00-LA33)
• 24 HA pairs (HA00-HA23)
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SW13 DIP Switch
Bus Width
Settings (M[2:0])
001 x1, x2, x4
101
[Ref 6]
CCLK Direction
Output
x1 Not Applicable
for further details on configuring
[Ref 19].
(Figure B-1) provides connectivity
(Table 1-26) implements a subset
AC701 Evaluation Board
UG952 (v1.4) August 6, 2019