Please Read: Important Legal Notices; Revision History - Xilinx VC707 User Manual

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Revision History

The following table shows the revision history for this document.
Date Version
03/05/12 1.0
10/08/12 1.1
VC707 Evaluation Board
IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx.
Initial Xilinx release.
Chapter 1, VC707 Evaluation Board
ASP_134486_01. The board photo in
was deleted. A note was added about the user clock for
AN1 changed to AM4 and pin AN2 changed to AM3. In
Generation, 25 MHz LVDS clock changed to 125 MHz LVDS clo ck. The
changed fr om 25 MHz to 125 MHz. In
switching regulator supply voltage UG63 for MGTVCCAUX was updated. In
type PTD08D021W (V A) power rail voltage changed to 1.80V. In
OUT
number 3 changed. In Appendix C, Xilinx Constraints
Appendix F, Regulatory and Compliance Information
Conformity and markings for waste electrical and electronic equipment (WEEE), restriction of
hazardous substances (RoHS), and CE compliance.
www.xilinx.com
Revision
Features: In Table 1-1, notes for J37 changed to Samtec
Figure 1-2 was replaced. In Table
Figure 1-10. In
SGMII GTX Transceiver Clock
Table 1-23, pin AR42 changed to AT42. In
File, the entire listing was replaced.
now includes a link to the Declaration of
UG885 (v1.8) February 20, 2019
1-3, GPGA (U1) Bank 32
Table 1-15, FPGA pin
Figure 1-10 title also
Figure 1-33,
Table 1-29, device
Table 1-32, values for rail