10 Mhz Timer; Adat Synchronization; Smpte Interface - Alesis ADAT BRC Service Manual

The 4053's in the VCO are used to lock the VCO to internal and external clock sources, thus
syncing all the other clocks. With the FPGA affecting the timing of the signal SLAVECLK (one of the
4053's controls) and with the H8/534 microprocessor affecting the signal FAST/SLOW (the other 4053's
control), the timing of the signal PCOUT, which pulses the gate of the FET, can be affected. This allows
the BRC to quickly lock its VCO to the incoming SMPTE clock.

2.3.2 10 MHZ Timer

The 10 MHZ timer (pin 3 of the H8/534 microprocessor) is used to help read the SMPTE data.
The basis for this clock is the 20 MHz crystal across pins 1 and 84 of the microprocessor. If there is a
problem in reading the SMPTE data, verify the 10 MHz's frequency. If the frequency is 10 MHZ, then
check the VCO circuit.

2.3.3 ADAT Synchronization

All ADAT syncing is done through the SYNC OUT circuit. The ADAT interfaces to the BRC
via the 9 pin Sync Out connector. Synchronization is achieved when the ADAT locks onto the 48 KHZ
signal being fed from the BRC through pin 26 of U11. The signal TCOUT provides all time code
information to the ADAT via pin 8 of J10. All communication from the ADAT, as well as information
about the ADAT's current location and mode of operation, is received through the signal line RXD2,
which runs from pins 2 and 6 of J10, through opto-isolator U12, to pin 78 on U10. Finally, all
information to the ADAT, with the exception of the time code information, is transmitted through the
signal line TXD2, which runs from pin 77 of U10, through 2 inverters (U15E and U14F), and finally out
through pin 9 of J10.
Since the ADATs also uses opto-isolators as part of its sync input circuit, the BRC sends out
three 5V DC references through connector J10, pins 3, 4, and 5. These voltages feed the opto-isolators
within the ADAT for the signals 48 KHZ, TCOUT, and TXD2, respectively.

2.3.4 SMPTE Interface

Everything related to SMPTE time code within the BRC is processed by the H8/534
microprocessor using the FPGA. There are only direct traces between the FPGA and the H8/534. If a
problem with SMPTE is suspected within the BRC, and an input SMPTE signal is being fed into pin 50
of the FPGA, and if the SMPTE circuitry appears to work, then problem is either in the FPGA, H8/534,
the traces between the two devices, and/or the VCO circuit.
There are three signals associated with the SMPTE circuit: SMPTE LEV, SMPTE OUT, and
SMPTE ON/OFF. The signal SMPTE LEV, which can be monitored from pin 5 of U10, sets the level of
the SMPTE OUT. When utilizing the +4 dBu mode, the signal SMPTE LEV is a tri-state signal, whose
output level is 2.5V peak to peak. If the -10 dBV mode is being implemented, the output of SMPTE
LEV is 633 mV peak to peak. The signal SMPTE OUT can be found on pin 9 of U11 and represents all
SMPTE output data. Finally, the signal SMPTE ON/OFF, which is found on pin 76 of U10, will turn the
SMPTE output off by going low.
For more information on setting up SMPTE within the BRC, consult the latest version of the
BRC Reference Manual.
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