JVC TH-A10 Service Manual page 26

TH-A10
3. Pin function
No. Pin Name I/O
1 AINR I
2 ZEROR I
3 AINL I
4 ZEROL I
5 VREFR O
6 VREFL O
7 VCOM O
8 AGND -
9 VA -
10 VB -
11 TST2 I/O
12 TST3 I/O
13 VD -
14 DGND -
15 TST1 I
16 CMODE I
17 PD I
18 MCLK I
19 SCLK I
20 L/R I
21 SDT0 O
22 DIF0 I
23 DIF1 I
24 DIF2 I
1-26
Rch Analog Input Pin
Rch Zero Input Pin
Lch Analog Input Pin
Lch Zero Input Pin
Rch Vopltage Reference Output Pin. 2.5V
Normally connected to AGND with a 0.1uF ceramic capacitor
in parallel with an electrolytic capacitor less than 10uF.
Lch Vopltage Reference Output Pin. 2.5V
Normally connected to AGND with a 0.1uF ceramic capacitor
in parallel with an electrolytic capacitor less than 10uF.
Voltage Common Output Pin. 2.5V
Normally connected to AGND with a 0.1uF ceramic capacitor
in parallel with an electrolytic capacitor less than 10uF.
Analog Ground Pin
Analog Supply Pin, +5V
Substrate Voltage Supply Pin, +5V
Test Pins (Pull-down pin)
Must be left floating.
Digital power Supply Pin, +5V
Digital Ground Pin
Test Pin (Pull-down pin)
Must be left floating or connected to DGND.
Master Clock Select Pin
"L" : MCLK=256fs, "H" : MCLK=384fs
Power-Down Pin
When "H", the circuit is in power-down mode,Upon
returning to "L", the AK5330 starts an offset calibration
cycle.A calibration cycle should always be initiated after
power-up.
Master Clock Input Pin
Serial Data Clock Pin
Output data is clocked out on the falling edge of SCLK.
Input data is clocked in on the rising edge of SCLK. SCLK
requires a continuously supplied clock at any frequency from
32fs to 64fs.
Left/Right Channel Select Pin
The fs clock is input to this pin.
"H" : Lch, "L" : Rch
Serial Data Output Pin
Data bits are presented MSB first, in 2's complement format.
This pin is "L" in the power-down mode.
Serial Interface Format Pin
Correspond to 8 modes.
Function