Watchdog Timer - Texas Instruments TMS320F2837 D Series Workshop Manual And Lab Manual

Watchdog Timer

The watchdog timer is a safety feature, which resets the device if the program runs away or gets
trapped in an unintended infinite loop. The watchdog counter runs independent of the CPU. If
the counter overflows, a user-selectable reset or interrupt is triggered. During runtime the correct
key values in the proper sequence must be written to the watchdog key register in order to reset
the counter before it overflows.
Resets the C28x if the CPU crashes

Watchdog must be serviced or disabled

within 131,072 WDCLK cycles after reset
This translates to 13.11 ms with a 10 MHz

WDCLK
The watchdog timer provides a safeguard against CPU crashes by automatically initiating a reset
if it is not serviced by the CPU at regular intervals. In motor control applications, this helps
protect the motor and drive electronics when control is lost due to a CPU lockup. Any CPU reset
will set the PWM outputs to a high-impedance state, which should turn off the power converters in
a properly designed system.
The watchdog timer starts running immediately after system power-up/reset, and must be dealt
with by software soon after. Specifically, the watchdog must be serviced or disabled within 13.11
milliseconds (using a 10 MHz watchdog clock) after any reset before a watchdog initiated reset
will occur. This translates into 131,072 watchdog clock cycles, which is a seemingly tremendous
amount! Indeed, this is plenty of time to get the watchdog configured as desired and serviced. A
failure of your software to properly handle the watchdog after reset could cause an endless cycle
of watchdog initiated resets to occur.
TMS320F2837xD Microcontroller Workshop - System Initialization
Watchdog Timer
Watchdog counter runs independent of CPU

If counter overflows, a reset or interrupt is

triggered (user selectable)
CPU must write correct data key sequence

to reset the counter before overflow
Watchdog Timer
5 - 7