Watchdog Timer - Texas Instruments TMS320F28004x Technical Reference Manual

Watchdog Timer

2.9 Watchdog Timer
The watchdog module consists of an 8-bit counter fed by a prescaled clock (WDCLK, which is connected
to INTOSC1). When the counter reaches its maximum value, the module generates an output pulse 512
WDCLKs wide. This pulse can generate an interrupt or a reset. The CPU must periodically write a 0x55 +
0xAA sequence into the watchdog key register to reset the watchdog counter. The counter can also be
disabled.
The counter's clock is divided down from WDCLK by two dividers. The prescaler is adjustable from /1 to
/64 in powers of two. The pre-divider defaults to /512 for backwards compatibility, but is adjustable from /2
to /4096 in powers of two. This allows a wide range of timeout values for safety-critical applications.
Figure 2-11 shows the various functional blocks within the watchdog module.
WDCR.WDPRECLKDIV
WDCLK
WDCLK
(INTOSC1)
Divider
SYSRSn
WDKEY(7:0)
Watchdog
Key Detector
55 + AA
Generate
WDRSTn
512-WDCLK
WDINTn
Output Pulse
SCSR.WDENINT
2.9.1 Servicing the Watchdog Timer
The watchdog counter (WDCNTR) is reset when the proper sequence is written to the WDKEY register
before the 8-bit watchdog counter overflows. The WDCNTR is reset-enabled when a value of 0x55 is
written to the WDKEY. When the next value written to the WDKEY register is 0xAA, then the WDCNTR is
reset. Any value written to the WDKEY other than 0x55 or 0xAA causes no action. Any sequence of 0x55
and 0xAA values can be written to the WDKEY without causing a system reset; only a write of 0x55
followed by a write of 0xAA to the WDKEY resets the WDCNTR.
102
System Control
Figure 2-11. Watchdog Timer Module
WDCR.WDPS WDCR.WDDIS
Watchdog
Prescaler
Good Key
Bad Key
Copyright © 2015–2017, Texas Instruments Incorporated
WDCNTR
8-bit
Watchdog
Counter
Clear
Count
WDWCR.MIN
Watchdog
In Window
Window
Out of Window
Detector
Watchdog Timeout
SPRUI33 – November 4 2015 – Revised January 2017
www.ti.com
1-count
Overflow
delay
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