Table of Contents
Advertisement
Status Byte register
The Status Byte register group reports the conditions from the other status
registers. Clearing an event register from one of the other registers will clear
the corresponding bits in the Status Byte condition register. Data that is
waiting in the U3606B output buffer is immediately reported on the "Message
Available" bit (bit 4).
Bit definitions: Status Byte register
Bit number
0 Not used
1 Not used
2 Error queue
3 Questionable Data
summary
4 Message available
5 Standard Event summary
6 Master Status summary
7 Not used
The Status Byte condition register will be cleared when:
• you execute the clear status (*CLS) command, or
• you read the event register from one of the other register groups. (Only the
The Status Byte enable register is cleared when you execute the *SRE 0
command.
N O T E
U3606B Programmer's Reference
Decimal value
Definition
Not used
"0" is returned.
Not used
"0" is returned.
4
One or more errors have been stored in the Error Queue. Use the
SYSTem:ERRor? query to read and delete errors.
8
One or more bits are set in the Questionable Data register. Bits must be
enabled using the STATus:QUEStionable:ENABle command.
16
Data is available in the instrument output buffer.
32
One or more bits are set in the Standard Event register. Bits must be
enabled using the *ESE command.
64
One or more bits are set in the Status Byte Register and may generate a
Request for Service (RQS). Bits must be enabled using the *SRE
command.
Not used
"0" is returned.
corresponding bits are cleared in the condition register.)
Refer to
Chapter
333 for more details of the common commands mentioned above.
16, "IEEE-488.2 Common Commands," starting on page
Introduction to SCPI
SCPI Status System
1
15
Advertisement
Table of Contents
