Cpu Jtag Header Pinout; Cpu Jtag Connection To Fpga - Xilinx ML505 User Manual

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ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
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CPU JTAG Header Pinout

Figure 1-8 shows J12, the 16-pin header that can be used to debug the software operating in
the CPU with debug tools such as Parallel Cable IV or third party tools.

CPU JTAG Connection to FPGA

The connections between the CPU JTAG header (J12) and the FPGA are shown in
Table 1-22. These are attached to the PowerPC® 440 processor JTAG debug resources
using normal FPGA routing resources. The JTAG debug resources are not hard-wired to
particular pins and are available for attachment in the FPGA fabric, making it possible to
route these signals to the preferred FPGA pins.
Table 1-22: CPU JTAG Connection to FPGA
Pin Name
CPU_TDO
FPGA_SC0_B (CPU_TDI)
CPU_TRST_N
CPU_TCK
CPU_TMS
PC4_HALT_B
(CPU_HALT_N)
CPU_TMS
CPU_HALT_N
J12
15
16
GND
Figure 1-8: CPU JTAG Header (J12)
FPGA Pin (U1)
E7
AF21
V10
E6
U10
W9
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Detailed Description
CPU_TCK
CPU_TDI
CPU_TDO
1
2
CPU_TRST_N
CPU_VSENSE
UG347_07_111505
Connector Pin (J12)
1
3
4
7
9
11
41