Virtex-5 Fpga; Configuration; I/O Voltage Rails - Xilinx ML505 User Manual

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1. Virtex-5 FPGA

ML505/ML506/ML507 Evaluation Platform
UG347 (v3.1.1) October 7, 2009
Downloaded from Elcodis.com electronic components distributor
A Xilinx Virtex-5 FPGA is installed on the board. See
device details.

Configuration

The board supports configuration in all modes: JTAG, Master Serial, Slave Serial, Master
SelectMAP, Slave SelectMAP, Byte-wide Peripheral Interface (BPI) Up, BPI Down, and SPI
modes. See the "Configuration Options," page 53

I/O Voltage Rails

Table 1-1 summarizes the FPGA I/O voltage rail and the voltages applied to each bank.
Table 1-1: I/O Voltage Rail of FPGA Banks
FPGA Bank
0 3.3V
1 3.3V
2 3.3V
3 2.5V no DCI
4 3.3V no DCI
(1)
5 3.3V DCI with 49.9Ω resistors installed
6 3.3V (unused)
11 User selectable as 2.5V or 3.3V using jumper J20
12 3.3V DCI with 49.9Ω resistors installed
13 User selectable as 2.5V or 3.3V using jumper J20
15 1.8V DCI with 49.9Ω resistors installed
17 1.8V DCI with 49.9Ω resistors installed
18 3.3V no DCI
19 1.8V DCI with 49.9Ω resistors installed
20 3.3V DCI with 49.9Ω resistors installed
21 1.8V DCI with 49.9Ω resistors installed
22 3.3V DCI with 49.9Ω resistors installed
(1)
23 3.3V DCI with 49.9Ω resistors installed
25 3.3V (unused)
Notes:
1. Banks 5 and 23 are available on the ML507 only.
section for more information.
I/O Voltage Rail
www.xilinx.com
Detailed Description
Appendix A, "Board Revisions" for
17