Pin Function Description; K4S641632D (U2) - Denon DN-S700 Service Manual

K4S641632D (U2)

PIN FUNCTION DESCRIPTION

Pin Name
System clock
CLK
CS Chip select
CKE Clock enable
Address
A ~ A
0 11
BA ~ BA Bank select address
0 1
RAS Row address strobe
CAS Column address strobe
WE Write enable
L(U)DQM Data input/output mask
DQ ~ Data input/output
0 15
V /V Power supply/ground
DD SS
V /V Data output power/ground
DDQ SSQ
No connection
N.C/RFU
/reserved for future use
V 1
54
DD
DQ0 2
53
V 3
52
DDQ
DQ1 4
51
DQ2 5
50
V 6
49
SSQ
DQ3 7
48
DQ4 8
47
V 9
46
DDQ
DQ5 10
45
DQ6 11
44
V 12
43
SSQ
DQ7 13
42
V 14
41
DD
LDQM 15
40
WE 16
39
CAS 17
38
RAS 18
37
CS 19
36
BA0 20
35
BA1 21
34
A10/AP 22
33
A0 23
32
A1 24
31
A2 25
30
A3 26
29
V 27
28
DD
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
34
DN-S700
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
N.C/RFU
UDQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
54Pin TSOP (II)
A4
(400mil x 875mil)
V
SS
(0.8 mm Pin pitch)
Input Function
~ RA , Column address : CA
11
after the clock and masks the output.
SHZ
~ CA
0 7