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For U.S.A., Canada, Europe & Japan model SERVICE MANUAL DN-C640 MODEL NETWORKED CD PLAYER NETWORK CD PLAYER DN-C640 DISPLAY PITCH LOCK END MON TEXT - INDEX/DIR + PUSH LEVEL ENTER EJECT NETWORK MENU/STORE POWER ON/OFF UTILITY SHIFT CANCEL SKIP BACK...
1. TECHNICAL SPECIFICATIONS ■ GENERAL Disc type : Standard compact discs (12 cm and 8 cm) CD-R, CD-RW, DVD-R, DVD-RW, DVD+R, DVD+RW ■ AUDIO SECTION Audio channel : 2 channel stereo Frequency response : 10 to 20,000Hz ±1.0 dB Dynamic range : 98 dB Signal-to-noise Ratio : 104 dB (1kHz, 0 dB playback, A fi...
2. SERVICE モード 2. SERVICE MODE 2.1 マイコンファームウェアのバージョン確認 2.1 Confi rming Microcomputer Firmware Version (フロントパネルを使って) [ Using the front panel ] 1. STOP モードでかつ、 SHIFT モードのときに、 MENU/ 1. While in stop and shift mode, press the MENU/STORE/ STORE/UTILITY ボタンを押します。 UTILITY button. 2.
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2.2 マイコンファームウェアの Update 2.2 Microcomputer Firmware Update Version Up ファイルが記録されたディスクを使用して、 マイ Use the disc that holds the Version Up fi le to rewrite the コンのファームを書き換えます。 microcomputer fi rmware. 1. Version Up フ ァ イ ル (DNC640up.bin) が 記 録 さ れ た 1.
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2.3 Confi rming DVD-ROM drive Firmware Version 2.3 DVD-ROMドライブのファームウェアのバージョン確認 (フロントパネルを使って) [ Using the front panel ] 1. STOP モードでかつ、 SHIFT モードのときに、 MENU/ 1. While in stop and shift mode, press the MENU/STORE/ STORE/UTILITY ボタンを押します。 UTILITY button. 2. Drive version がディスプレイに表示されるまでジョグ 2.
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2.4 DVD-ROM ドライブのファームウェアの Update 2.4 DVD-ROM Drive Firmware Update Version Up フ ァ イ ル が 記 録 さ れ た デ ィ ス ク (CD-ROM Use the disc (CD-ROM MODE1, ISO9660 LEVEL1) that MODE1, ISO9660 LEVEL1) を使用して、 DVD-ROM ドライ holds the Version Up fi...
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POS. VERS. PART NO. PART NO. PART NAME DESCRIPTION NAME COLOR (FOR EUR) (D&M) 004B 00M238H355020 00M238H355020 LENS LENS FOR POWER SW 008B 00M43BS355012 00M43BS355012 LENS IR LENS 010B 00M43BS105023 00M43BS105023 CHASSIS FRONT INNER MOLD 012B 00M43BS303010 00M43BS303010 MASK MASK FOR CD 014B 00M43BS160030 00M43BS160030 BRACKET FRONT BRACKET...
8. MICROPROCESSOR AND IC DATA 8.1 Microprocessor Q018 : EP9312 - CBZ-E1 DN-C640 PORT Connection Function I/O DET Ext CSN[7] CSN7 – – No Use DA[28] DA28 – – – Memory Data Bus 28 ROM/RAM AD[18] AD18 – – –...
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Q018 : EP9312 - CBZ-E1 DN-C640 PORT Connection Function I/O DET Ext DA[25] DA25 − − − Memory Data Bus 25 ROM/RAM DD[11] DD11 − − − IDE Data Bus 11 SDCLKEN SDCLKEN − − − − SDRAM SDCLKEN SDRAM...
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8.2 IC DATA Q001, Q002, Q003, Q004, Q006, Q011, Q405, Q703 : NJM2387DL2 PIN FUNCTION 2.ON/OFF CONTROL 5.GND 1 2 3 4 5 NJM2387DL2 EQUIVALENT CIRCUIT Bandgap Reference ON/OFF Control control Over Voltage Thermal Over Current Protection Protection Protection NJM2387DL2 Q005, Q026, Q028, Q030, Q300, Q501, Q712 : SN74LV125APW FUNCTION TABLE (TOP VIEW)
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Q009 : S-24C04BFJ (TOP VIEW) Function Number Name ∗ ∗ ∗ ∗ 1 No Connection ∗ ∗ ∗ ∗ 1 No Connection ∗ ∗ ∗ ∗ 1 No Connection Ground Serial data input/output Serial clock input Write Protection pin Figure 2 Connected to Vcc: Protection valid Connected to GND: Protection invalid S-24C01BFJ...
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Q022 : JS28F128P30T85 56-Lead TSOP Pinout (64/128/256-Mbit) WAIT A 16 A 17 DQ15 DQ14 DQ13 DQ12 ADV# Intel StrataFlash Æ Embedded Memory (P 30) RST# 56-Lead TSOP Pinout DQ11 14 mm x 20 mm DQ10 Top View VCCQ OE # Notes: A1 is the least significant address bit.
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Q022 : JS28F128P30T85 Symbol Type Name and Function ADDRESS INPUTS: Device address inputs. 64-Mbit: A[22:1]; 128-Mbit: A[23:1]; 256-Mbit: A[24:1]; A[MAX:1] Input 512-Mbit: A[25:1]. DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during Input/ DQ[15:0] memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls Output float when the CE# or OE# are deasserted.
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Q024 : BD45302G-TR Pin No. Pin Name Q025, Q036 : SN74LV00APW (TOP VIEW) FUNCTION TABLE (each gate) INPUTS OUTPUT OUTPUT LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)
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Q031 : CS4271-CZZR 3.3 V to 5 V 2.5 V to 5 V Hardware or Left and Internal Voltage Internal External C/SPI Right Mute Reference Oscillator Mute Control Control Data Controls Register / Hardware Configuration Reset Selectable Left Volume Switched Capacitor ∆Σ...
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Q031 : CS4271-CZZR Pin Name Pin Description Crystal Connections (Input/Output) - I/O pins for an external crystal which may be used to generate MCLK. See “Crystal Applications (XTI/XTO)” on page 24 or “Crystal Applications (XTI/XTO)” on page 27. Master Clock (Input/Output) -Clock source for the delta-sigma modulators. See “Crystal Applications MCLK (XTI/XTO)”...
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Q032 : CS8420-CSZR VA+ AGND FILT RMCK VD+ DGND RERR ILRCK OLRCK Serial Sample Serial ISCLK OSCLK Audio Rate Audio Input Converter Output SDIN SDOUT Clock & AES3 C & U bit AES3 Receiver Driver Data S/PDIF Data S/PDIF Recovery Decoder Buffer Encoder...
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Q034, Q035 : NJU3716AM-TE1 DATA DATA Controller Circuit TERMINAL DESCRIPTION SYMBOL FUNCTION Parallel Conversion Data Output Terminals Parallel Conversion Data Output Terminals Serial Data Output Terminal DATA Serial Data Input Terminal Clock Signal Input Terminal Strobe Signal Input Terminal Clear Signal Input Terminal Parallel Conversion Data Output Terminal Parallel Conversion Data Output Terminals Power Supply Terminal (2.4 to 5.5V)
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Q037, Q038 : SN74LV138APW (TOP VIEW) FUNCTION TABLE ENABLE INPUTS SELECT INPUTS OUTPUTS LOGIC DIAGRAM (POSITIVE LOGIC) Select Inputs Data Outputs Enable Inputs Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.
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Q039 : SN74LV541APW (TOP VIEW) LOGIC DIAGRAM (POSITIVE LOGIC) To Seven Other Channels FUNCTION TABLE (each buffer/driver) INPUTS OUTPUT OUTPUT Q040, Q041 : SN7438NSR (TOP VIEW) LOGIC DIAGRAM FUNCTION TABLE (each gate)
Q042 : 78Q2120C09A-64GCT BLOCK DIAGRAM 4 B / 5 B E n c o d e r , 1 0 0 M N R Z / N R Z I , Scrambler, MTL3 Encoder Parallel/Serial Pulse Shaper TXOP & Filter Drivers T X C l o c k T X O N...
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Q042 : 78Q2120C09A-64GCT PIN DESCRIPTION LEGEND TYPE DESCRIPTION TYPE DESCRIPTION Analog Pin Digital Input Digital Output Digital Bi-directional Pin Supply Tri-stateable digital output MII (MEDIA INDEPENDENT INTERFACE) 64-PIN 80-PIN TYPE DESCRIPTION TX_CLK TRANSMIT CLOCK: TX_CLK is a continuous clock w hich provides a timing reference for the TX_EN, TX_ER and TXD[3:0] signals from the MAC.
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Q042 : 78Q2120C09A-64GCT (continued) 64-PIN 80-PIN TYPE DESCRIPTION MANAGEMENT DATA CLOCK: clock used transferring data via the MDIO pin. MDIO MANAGEMENT DATA INPUT/OUTPUT: MDIO is a bi-directional port used to access management registers within the 78Q2120. This pin requires an external pull-up resistor as specified in IEEE-802.3. PHY ADDRESS PHYAD[4:0] 12-16...
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Q042 : 78Q2120C09A-64GCT CONTROL AND STATUS (continued) 64-PIN 80-PIN TYPE DESCRIPTION ANEGA AUTO-NEGOTIATION ABILITY: Strapped to logic high to allow auto- negotiation function. When strapped to logic low, auto-negotiation logic is disabled and manual technology selection is done through TECH[2:0]. This pin is reflected as ANEGA bit (MR1.3). TECHNOLOGY ABILITY/SELECT: TECH[2:0] sets the technology ability of the TECH[2:0] 44-46...
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Q042 : 78Q2120C09A-64GCT OSCILLATOR/CLOCK NAME 64-PIN 80-PIN TYPE DESCRIPTION CKIN CLOCK INPUT: Connects to a 25 MHz clock source. This pin should be held low when XTLP and XTLN are being used as the 25 MHz clock source. XTLP, 59, 58 75,74 CRYSTAL PINS: Should be connected to a 25 MHz crystal.
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Q704 : BD9781HFP ON/OFF EN/SYNC L : OFF H : ON SOFT Vref SYNC START ERROR AMP COMPARATR LATCH DRIVER RESET CURRENT LIMT Pin No. Pin Name EN/SYNC...
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Q709 : µPD78F9222 NOTE P121/X1 P20/ANI0 P122/X2 P21/ANI1 P123 P22/ANI2 P23/ANI3 P130 RESET/P34 P31/T1010/TO00/INTP2 P30/TI000/INTP3 P44/RxD6 P43/TxD6INTP1 P41/INTP3 P42/TOH1 ANI0 to ANI3: Analog input RESET: Reset Analog reference voltage RxD6: Receive data INTP0 to INTP3: External interrupt input TI000, TI010: Timer input P20 to P23: Port 2...
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Q709 : µPD78F9222 (1) Port functions Pin Name Function After Reset Alternate- Function Pin P20 to P23 Port 2. Input ANI0 to ANI3 4-bit I/O port. Can be set to input or output mode in 1-bit units. An on-chip pull-up resistor can be connected by setting software. Port 3 Can be set to input or output mode in 1- Input...
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Q709 : µPD78F9222 (2) Non-port functions Pin Name Function After Reset Alternate- Function Pin INTP0 Input External interrupt input for which the valid edge (rising edge, Input P30/TI000 falling edge, or both rising and falling edges) can be specified INTP1 P43/TxD6 INTP2 P31/TI010/TO00...