Xtsl - Denon DN-S700 Service Manual

Power Pin
Symbol
supply No.
70 IOV 2
DD
Digital 71 DOUT
I/O = 3.3V
72 TEST
Internal =
73 TES1
2.5V
74 IOVss2
— 75 NC
76 XV
SS
77 XTAO
X'tal
2.5V
78 XTAI
79 XV
DD
80 AV 1
DD
81 AOUT1
Lch
3.3V
82 VREFL
83 AV 1
SS
84 AV 2
SS
85 VREFR
Rch
3.3V
86 AOUT2
87 AV 2
DD
— 88 NC
89 IOV 0
DD
90 RMUT
91 LMUT
92 NC
93

XTSL

94 IOV 0
SS
95 XTACN
Digital
I/O = 3.3V
96 SQSO
Internal =
2.5V
97 SQCK
98 SBSO
99 EXCK
100 XRST
101 SYSM
102 DATA
103 V
SS
104 XLAT
I/O
— — I/O digital power supply.
O 1, 0 Digital Out output.
I Test pin. Normally GND.
I Test pin. Normally GND.
— — I/O digital GND.
— —
— — Master clock GND.
O Crystal oscillation circuit output.
I Crystal oscillation circuit input.
— — Master clock power supply.
— — Analog power supply.
O Lch analog output.
O Lch reference voltage.
— — Analog GND.
— — Analog GND.
O Rch reference voltage.
O Rch analog output.
— — Analog power supply.
— —
— — I/O digital power supply.
O 1, 0 Rch "0" detection flag.
O 1, 0 Lch "0" detection flag.
— —
Crystal selection input.
I Low when the crystal is 16.9344MHz;
high when the crystal is 33.8688MHz.
— — I/O digital GND.
Oscillation circuit control.
I
Self-oscillation when high, oscillation stop when low.
Subcode Q 80-bit and PCM peak and level data output.
O 1, 0
CD TEXT data output.
I SQSO readout clock input.
O 1, 0 Subcode P to W serial output.
I SBSO readout clock input.
I System reset. Reset when low.
I Mute input. Muted when high.
I Serial data input from CPU.
— — Internal digital GND.
I Latch input from CPU. The serial data is latched at the falling edge.
DN-S700
Description
20