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5. Frequency Synthesizer Circuit
The frequency synthesizer consists of the TCXO (X1),
VCO, PLL IC (IC1) and buffer amplifi ers.
The TCXO generates 16.8MHz. The frequency stability
is 1.0ppm within the temperature range of –30 to +60°C.
The frequency tuning and modulation of the TCXO are done
to apply a voltage to pin 1 of the TCXO. The output of the
TCXO is applied to pin 8 of the PLL IC.
The VCO consists of 2VCO and covers a dual range of
the 305.15~345.15MHz and the 350~390MHz. The VCO
generates 305.15~345.15MHz for providing to the fi rst local
signal in receive. The operating frequency is generated by
Q3 in transmit mode and Q2 in receive mode. The oscillator
frequency is controlled by applying the VCO control voltage,
obtained from the phase comparator (IC1) to the variable ca-
pacitor diodes (D1 and D3 in transmit mode and D2 and D4
in receive mode).
The T/R pin of IC312 goes "high" in receive mode caus-
ing Q4, Q6 and Q3 turn off, and Q2 turn on. The T/R pin
goes "low" in transmit mode.
The outputs from Q2 and Q3 are amplifi ed by buffer am-
plifi er (Q5) and doubled by Q1 and then sent to PLL IC.
The PLL IC consists of a prescaler, reference divider,
phase comparator, charge pump (The frequency step of the
PLL circuit is 12.5kHz). The input signal from the pins 8 and
5 of the PLL IC is divided down to the 12.5kHz and com-
pared at phase comparator. The pulsed output signal of the
phase comparator is applied to the charge pump and trans-
formed into DC signal in the loop fi lter (LPF). The DC signal
is applied to the CV of the VCO and locked to keep the VCO
frequency constant.
PLL data is output from DP (pin 73), CP (pin 74) and EP
(pin 72) of the MCU (IC309). The data are input to the PLL
IC when the channel is changed or when transmission is
changed to reception and vice versa. A PLL lock condition is
always monitored by the pin 30 (UL) of the MCU. When the
PLL is unlocked, the UL goes low.
CIRCUIT DESCRIPTION /
T/R
T/R
VCO
(TX : Low)
CV
Doubler
LPF
IC1
20
5
PLL
15
8
UL
MCU
DP,CP,EP
IC309
Fig. 8 PLL block diagram / 图 8 PLL 方块图
电路说明
5. 频率合成器电路
频率合成器由 TCXO(X1)、VCO、PLL IC(IC1) 和缓冲放大器
组成。
TCXO 产生 16.8MHz 的频率。在温度为 -30~+60℃的范围内，
频率的稳定性为 1.0ppm。进行频率调谐和 TCXO 调制，以便给
TCXO 的针脚 1 提供电压。 TCXO 的输出加在 PLL IC 的针脚 8 上。
VCO 由 2VCO 组成，并且覆盖了 305.15~345.05MHz 和 350~
390MHz 双波段。VCO 产生 305.15~345.05MHz 的频率，以提供
接收的第一个本振信号。发射模式时，操作频率由 Q3 产生，
而接收模式时，操作频率由 Q2 产生。振荡频率由加在 V C O 上
的控制电压控制，控制电压从可变电容二极管 ( 在发射模式
是 D1 和 D3，在接收模式是 D2 和 D4) 的相位比较器 ( I C1) 处
获得。
I C312 的 T / R 针脚在接收模式时为"高"电位，使 Q4、Q6
和 Q3 关断，Q2 打开。T/R 针脚在发射模式时为"低"电位。
Q2 和 Q3 的输出由缓冲放大器 ( Q5) 放大，并由 Q1 倍频，
然后发送到 PLL IC。
P L L I C 由预计数器、基准除法器、相位比较器、电荷泵
组成 (PLL 电路的频率步长为 12.5kHz)。PLL IC 的针脚 8 和
5 的输入信号下分成 12.5k H z，并在相位比较器处进行比较。
相位比较器的脉冲输出信号加在电荷泵上，并转换成环路滤
波器 (LPF) 的 DC 信号。DC 信号加在 VCO 的 CV 上并锁定，使
VCO 的频率恒定。
PLL 数据从 MCU(IC309) 的 DP( 针脚 73)，CP( 针脚 74) 和
EP( 针脚 72) 输出。当信道改变时，或当由发射变为接收或由
接收变为发射时，数据输入 P L L I C。P L L 的锁定条件总是由
MCU 的针脚 30(UL) 监控。当 PLL 失锁时，UL 为低电位。
Q8
D101
To
BUFF
SW
drive
amp
D100
SW
x2
Q1
To mixer
FC
VC
TCXO
IC302
X1
BAL
TK-3148
15
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