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Circuit Description
The transmit signal then passes through the antenna switch
D1004 (RLS135) and is low-pass filtered to suppress har-
monic spurious radiation before delivery to the antenna.
CTCSS/DCS Signal Path
If a CTCSS tone encoder is enabled, the CTCSS tone gen-
erated by Q1013 (M37516F8HP), then delivered to VCO
Q1003 (2SC5231) and TCXO X1001 for CTCSS modulat-
ing.
If a DCS encoder is enabled, the DCS code is generated by
microprocessor Q1013 (M37516F8HP), then delivered to
TCXO X1001 for DCS modulating.
Automatic Transmit Power Control
Current from the final amplifier is sampled by R1136,
R1139 and R1142, and is rectified by Q1029 (IMZ2A). The
resulting DC is fed through the Automatic Power Con-
troller Q1031 (FMW1) to the drive amplifier Q1019
(RD01MUS1) and final amplifier Q1024 (RD07MVS1), for
control of the power output.
Transmit Inhibit
When the transmit PLL is unlocked, pin 7 of PLL IC Q1005
(MB15A02PFV1) goes to logic "Low", and unlock detec-
tor Q1010 (2SA1586) goes to logic "High". The resulting
DC unlock control voltage is passed to pin 14 of the mi-
croprocessor Q1013 (M37516F8HP). While the transmit
PLL is unlocked, pin 22 of Q1013 (M37516F8HP) remains
high, which turns off Q1020 (CPH6102) and the Auto-
matic Power Controller Q1031 (FMW1) to disable the sup-
ply voltage to the drive amplifier Q1019 (RD01MUS1) and
final amplifier Q1024 (RD07MVS1), thereby disabling the
transmitter.
Spurious Suppression
Generation of spurious products by the transmitter is min-
imized by the fundamental carrier frequency being equal
to final transmitting frequency, modulated directly in the
transmit VCO. Additional harmonic suppression is pro-
vided by a low-pass filter consisting of coils L1003 and
L1006, capacitors C1009, C1012, C1020, C1023, and C1030,
resulting in more than 60 dB of harmonic suppression
prior to delivery to the antenna.
10
PLL Frequency Synthesizer
The PLL circuitry on the Main Unit consists of VCO Q1003
(2SC5231), VCO buffer Q1006 (2SC5005), and PLL IC
Q1005 (MB15A02PFV1) which contains a reference divid-
er, serial-to-parallel data latch, programmable divider,
phase comparator and charge pump.
While receiving, VCO Q1003 (2SC5231) oscillates be-
tween 194.25 and 218.25 MHz according to the pro-
grammed receiving frequency. The VCO output is buff-
ered by Q1006 (2SC5005), then applied to the prescaler
section of Q1005 (MB15A02PFV1). There the VCO signal
is divided by 64 or 65, according to a control signal from
the data latch section of Q1005 (MB15A02PFV1), before
being sent to the programmable divider section of Q1005
(MB15A02PFV1).
The data latch section of Q1005 (MB15A02PFV1) also re-
ceives serial dividing data from the microprocessor Q1013
(M37516F8HP), which causes the pre-divided VCO sig-
nal to be further divided in the programmable divider
section, depending upon the desired receive frequency,
so as to produce a 2.5 kHz, 5 kHz, or 6.25 kHz derivative
of the current VCO frequency.
Meanwhile, the reference dividers section of Q1005 di-
vides 14.60 MHz reference frequency from the TCXO Unit
X1001, by 5840 (or 2920 or 2336) to produce the 2.5 kHz
(or 5 kHz or 6.25 kHz) loops reference (respectively).
The 2.5 kHz (or 5 kHz or 6.25 kHz) signal from the pro-
grammable divider (derived from the VCO) and that de-
rived from the reference oscillator are applied to the phase
detector section of Q1005 (MB15A02PFV1), which pro-
duces a pulsed output with pulse duration depending on
the phase difference between the input signals.
This pulse train is filtered to DC and returned to the var-
actor diodes D1001 (HVC358B) and D1002 (HVC355B).
Changes in the level of the DC voltage applied to the var-
actor diodes, affecting the reference in the tank circuit of
the VCO according to the phase difference between the
signals derived from the VCO and the TCXO Unit X1001.
The VCO is thus phase-locked to the crystal reference os-
cillator. The output of the VCO Q1003 (2SC5231), after
buffering by Q1006 (2SC5005), is applied to the 1st mixer
as described previously.
For transmission, the VCO Q1003 (2SC5231) oscillates
between 150 and 174 MHz according to the programmed
transmit frequency. The remainder of the PLL circuitry is
shared with the receiver. However, the dividing data from
the microprocessor is such that the VCO frequency is at
the actual transmit frequency (rather than offset for IFs,
as in the receiving case). Also, the VCO is modulated by
the speech audio applied to D1005 (HVC350), as described
previously.
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