System Configuration; Software Applications - Xilinx MicroBlaze Spartan-3E 1600E Edition Getting Started

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System Configuration

This reference system runs off a reference clock frequency of 66.67MHz from the auxiliary
oscillator on the board. The OPB BUS, Ethernet MAC, and the MicroBlaze processor run at
66.67MHz, while the DDR runs at 133MHz.
The MicroBlaze Development Kit Spartan-3E 1600E Edition Board User Guide, which is a part
of the Development Kit Reference CD supplied with this kit, provides additional
information on board specifics and UCF location constraints for the different cores used in
this reference system.
MicroBlaze Processor Configuration
The MicroBlaze with MCH OPB DDR is configured with the I-cache and D-cache enabled.
A cache size of 8KB is set for both the instruction cache (I-cache) and the data cache (D-
cache). The cacheable block of main memory resides between 0x22000000 and
0x2200FFFF. The MCH interfaces of the MCH OPB DDR memory controller are
connected to the MicroBlaze processor and configured to use the XCL protocol.
The Instruction Cache and Data Cache sections in the MicroBlaze Processor Reference Guide
provide details on the MicroBlaze processor caches.
OPB Ethernet Configuration
The µClinux RTOS requires that the OPB Ethernet be set to use Scatter-Gather DMA
capability and that the interrupts be set to on. In the µClinux demonstration, the Ethernet
MAC can run at 10 Mb/s or 100 Mb/s, depending on the attached network. No other
special settings are needed.
OPB EMC Configuration
The OPB EMC memory controller is connected to an external Intel StrataFlash PROM,
which is used to store the hardware configuration bitstream and bootloader application, as
well as the µClinux kernel image file.
OPB UART Lite Configuration
The OPB UART Lite core is configured to use interrupts. It is set up to use the DTE-Style
serial port with the baud rate set to 115200. This requires the use of the Null-modem serial
cable provided with this Kit.

Software Applications

The software sources and executable files for simple memory and peripheral tests have
been provided for use in basic functional testing.
Getting Started with the MicroBlaze Development Kit - Spartan3E 1600E Edition
UG258 (v1.0) June 29, 2006
The source code for the memory and peripheral tests are located under the project root
directory as /TestApp_Memory/src/TestApp_Memory.c and
/TestApp_Peripheral/src/TestApp_Peripheral.c, respectively.
The executable files for these tests are located under the project root directory as
/TestApp_Memory/executable.elf and
/TestApp_Peripheral/executable.elf, respectively.
www.xilinx.com
Software Applications
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