Fpga Mezzanine Card Interface - Xilinx ZCU111 User Manual

FPGA Mezzanine Card Interface

[Figure 2-1, callouts 33,34]
The ZCU111 evaluation board supports the VITA 57.4 FPGA mezzanine card (FMC+ or
FMCP) specification by providing a subset implementation of the high pin count connector
at J26 (HSPC). FMC+ connectors use a 14 x 40 form factor, populated with 560 pins. The
connector is keyed so that a mezzanine card, when installed on the ZCU111 evaluation
board, faces away from the board
J26 FMC+ Connector Type
• Samtec SEAF series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector. For
more information about SEAF series connectors, see the Samtec website
more information about the VITA 57.4 FMC+ specification, see the VITA FMC Marketing
Alliance website
• The 560-pin FMC+ connector defined by the FMC specification (see
57.4 FMCP Connector
160 single-ended or 80 differential user-defined signals
°
24 transceiver differential pairs
°
6 transceiver differential clocks
°
4 differential clocks
°
239 ground and 19 power connections
°
FMCP Connector J26
[Figure 2-1, callout 27]
The HSPC connector J26 implements a subset of the full FMCP connectivity:
• 68 single-ended or 34 differential user-defined pairs (34 LA pairs: LA[00:33])
• 12 transceiver differential pairs
• 3 transceiver differential clocks
• 2 differential clocks
• 239 ground and 16 power connections
The FMCP HSPC J26 connections to RFSoC U1 are referenced in
Constraints. See the FPGA Mezzanine Card (FMC) VITA 57.4 specification
additional information on the FMCP HSPC connector.
ZCU111 Board User Guide
UG1271 (v1.1) August 6, 2018
[Ref 23].
Pinouts) provides connectivity for up to:
www.xilinx.com
Chapter 3: Board Component Descriptions
Appendix A, VITA
Appendix B, Xilinx Design
[Ref 23]
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