Samsung SF-4500 Service Manual page 33

6-1-2 MFP Controller (KS32C6200 : U16)
MFP Controller consists of CPU(ARM7TDMI RISC
processor), 2K-byte cache, data and address buses,
serial communication part with LIU(Line Interface
Unit), OPE(OPERATION PANEL) print head con-
troller, parallel port interface, external DMA part to
receive data from external color image processor
(SCANIP:U18), LF/CR motor diver
controller and I/O controller.
6-1-2-1. SYSTEM CLOCK
The internal clock frequency is 30MHz. 30MHz
system clock (MCLK) supplied from the outside is
used without being divided inside.
6-1-2-2. DATA & ADDRESS BUS CONTROL
• /RD & /WR
/RD & /WR signals are synchronized with
MCLK(30MHz) and become LOW ACTIVE.
These signals are strobe signals used to read and
write data when each CHIP SELECT is connected
6-2
with /RD and /WR pin of RAM, ROM, MODEM
and the outside devices and becomes active.
• CHIP SELECT (/IP_CS, /ROMCS, /MCS /
RAMCS)
- /IP-CS : SCANIP(U18) CHIP SELECT (LOW
ACTIVE)
- /ROMCS : ROM/FLASH MEMORY(U5) CHIP
SELECT (LOW ACTIVE)
- /MCS : MODEM(U15) CHIP SELECT (LOW
ACTIVE)
- /RAMCS : SRAM (U14) CHIP SELECT (LOW
ACTIVE)
When each CHIP SELECT is low, data can be read or
written.
• D0 - D15
- 16bit data bus
• A0 - A17
- ADDRESS BUS (A18 - A21 are reserved.)
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