W9825G6Eh-6J Pin Description - Marantz SR7005 Service Manual

W9825G6EH-6J Pin Description

PIN NUMBER
23 26, 22,
29 36
20, 21
2, 4, 5, 7, 8, 10,
11, 13, 42, 44,
45, 47, 48, 50,
51, 53
19
18
17
16
15, 39
38
37
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
40
PIN NAME FUNCTION
A0 A12 Address
BS0, BS1 Bank Select
Data
DQ0 DQ15
Input/Output
Chip Select
CS
Row Address
RAS
Strobe
Column
Address
CAS
Strobe
Write Enable Referred to RAS
WE
LDQM, Input/Output
UDQM Mask
CLK Clock Inputs
CKE Clock Enable
V Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
CC
V Ground
SS
Power (+3.3V)
V
CCQ
for I/O Buffer
Ground
V
SSQ
for I/O Buffer
NC No Connection
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0 A12. Column address: A0 A8.
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock, RAS , CAS and WE define the operation
to be executed.
Referred to RAS
The output buffer is placed at Hi-Z(with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write operation
with zero latency.
System clock used to sample inputs on the rising edge
of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend mode,
or Self Refresh mode is entered.
Ground for input buffers and logic circuit inside DRAM.
Separated power from V
CC
immunity.
Separated ground from V
immunity.
No connection. (NC pin should be connected to GND
or floating)
162
, to improve DQ noise
, to improve DQ noise
SS