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Circuit Description
Table 1-1 KS32C6100 Signal Descriptions (Cont.)
SIGNAL
PIN No.
GPIO[11 ] :
188
n C P U P W R
GPIO[10]:
187
PPDOE
GPIO[9]:
1 8 6
ExtlACK1
GPIO[8]:
185
ExtlACK0
GPIO[7]:
182
ExtlREQ1
GPIO[6]:
181
ExtlREQ0
GPIO[5]:
180
ExtDACK2
GPIO[4]:
179
ExtDACK1
GPIO[3]:
178
ExtDACK0
GPIO[2]:
177
ExtDREQ2
GPIO[2]:
176
ExtDREQ1
GPIO[2]:
175
ExtDREQ0
NOTE: The I/O port pin assignments described in this table are p resented as only one example.
You can modify the port map as necessary in order to meet the requirements of a specific application.
5-14
Type
O
KS32C6100 power ready. nCPUPWR is a status nCPUPWR signal
that is output to the laser printer engine. Actually, any I/O port pin
can be mapped to output this signal without any modifications.
O
Parallel data output enable. When PPDOE is PPDOE "1", the
parallel port data bus, PPD[7:0], is in output mode. Otherwise it is
in input mode.
O
I n t e r rupt acknowledge for external ExtiACK1 interru p t request
ExitREQ1.
O
I n t e r rupt acknowledge for external interrupt ExtiACK0 request
ExitREQ0.
I
External interru p t request input 1. For a valid ExtiREQ1 re q u e s t ,
this signal must be held active for at least four machine cycles.
I
External interru p t request input 0. For a valid re q u e s t , t h i s
signal must be held active for at least four machine cycles.
O
D M A acknowledge for external DMA2 request . The active
output signal is generated whenever a DMA transfer on GDMA1 is
completed.
O
D M A acknowledge for external DMA1 request . The active
output signal is generated whenever a DMA transfer on GDMA0 is
completed.
O
D M A acknowledge for external DMA0 request . The active
output signal is generated whenever a DMA transfer on GDMA i s
completed.
I
External DMA2(GDMA1) request. ExtDREQ2 is asserted by a
peripheral device to request a data transfer using GDMA1. This
signal must be held active for at least four machine cycles.
I
External DMA1(GDMA0) request. ExtDREQ1 is asserted by a
peripheral device to request a data transfer using GDMA0. This
signal must be held active for at least four machine cycles.
I
External DMA0(GDMA) request. ExtDREQ0 is asserted by a
peripheral device to request a data transfer using GDMA. This
signal must be held active for at least four machine cycles.
Description
Samsung Electronics
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